Three dimensional structure memory
First Claim
1. An apparatus comprising:
- a first integrated circuit having a thickness Th1;
a second integrated circuit having a thickness Th2; and
a large number of vertical interconnect segments interconnecting the first and second integrated circuits;
wherein the interconnect segments have lengths of about Th1+Th2 or less.
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
171 Citations
58 Claims
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1. An apparatus comprising:
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a first integrated circuit having a thickness Th1; a second integrated circuit having a thickness Th2; and a large number of vertical interconnect segments interconnecting the first and second integrated circuits;
wherein the interconnect segments have lengths of about Th1+Th2 or less. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 47, 55, 56)
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8. An apparatus comprising:
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a first integrated circuit layer having a thickness Th1; a second integrated circuit layer having a thickness Th2; and a plurality of interconnect segments interconnecting the first and second integrated circuit layers; wherein the interconnect segments have lengths of about Th1+Th2 or less. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 51, 52, 53, 54, 57, 58)
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Specification