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Three dimensional structure memory

  • US 20090219772A1
  • Filed: 03/17/2009
  • Published: 09/03/2009
  • Est. Priority Date: 04/04/1997
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a first integrated circuit having a thickness Th1;

    a second integrated circuit having a thickness Th2; and

    a large number of vertical interconnect segments interconnecting the first and second integrated circuits;

    wherein the interconnect segments have lengths of about Th1+Th2 or less.

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