Wide bandgap transistor devices with field plates
First Claim
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1. A transistor, comprising:
- a plurality of active semiconductor layers on a substrate;
a source contact in electrical contact with said plurality of active layers;
a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers;
a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts;
a spacer layer covering said gate and substantially all of the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts; and
a field plate formed on said spacer layer and electrically connected to said gate by one or more conductive paths running outside said plurality of active layers.
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Abstract
A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.
45 Citations
25 Claims
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1. A transistor, comprising:
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a plurality of active semiconductor layers on a substrate; a source contact in electrical contact with said plurality of active layers; a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers; a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer covering said gate and substantially all of the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts; and a field plate formed on said spacer layer and electrically connected to said gate by one or more conductive paths running outside said plurality of active layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A transistor, comprising:
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a plurality of Group-III nitride active semiconductor layers; a source contact in electrical contact with said plurality of active layers; a drain contact in electrical contact with said plurality of active layers with space between said source and drain contacts on said plurality of active layers; a gate contact in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer covering at least one of said contacts; and a field plate on said spacer layer and electrically connected to at least one of said contacts by one or more conductive paths running outside said plurality of active semiconductor layers. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A transistor, comprising:
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a plurality of active semiconductor layers on a substrate; a source contact in electrical contact with said plurality of active layers; a drain contact also in electrical contact with said plurality of active layers with space between said source and drain contacts on the topmost of said plurality of active layers; a gate in electrical contact with said topmost of said plurality of active layers, between said source and drain contacts; a spacer layer on and covering substantially all of the surface of the topmost of said plurality of active layers, between said gate and said source and drain contacts, wherein said gate is not covered by said spacer layer; and a field plate on said spacer layer integral to said gate, wherein said field plate at least partially overlaps said gate and extends on said spacer layer a distance Lf toward said drain contact.
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Specification