Vehicle Computer System with Audio Entertainment System

• US 20090228615A1
• Filed: 09/05/2008
• Published: 09/10/2009
• Est. Priority Date: 01/07/1998
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Li, Hang, Moeller, Mark M., Beckert, Richard D.
• Granted Patent: US 8,001,290 B2
• Time in Patent Office: Days
• US Class Current: 710/21
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2016/0322 Temporary code for documents to be reclassified to G08C, H04L or H04Q

Abstract

A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s). The computer system also supports a speech recognition system. Speech utterances are picked up by a microphone and sampled at an internal sampling rate. However, the speech recognition system employs a lower sampling rate. The computer system converts microphone data from the higher internal sampling rate to the desired sampling rate by piggybacking the microphone data on command/message streams to an SPI (serial peripheral interface) of the audio DSP. The DSP performs normal low-pass filtering and down sampling on the data stream and then uses the SPI to send out the microphone data at the lower sampling rate.

Claims

1. A vehicle computer system comprising:

an audio data processor;

an I/O memory;

a first memory access circuit associated with a first data source to transfer first audio data from the first data source to a first location in the I/O memory;

a second memory access circuit associated with a second data source to transfer second audio data from the second data source to a second location in the I/O memory; and

a third memory access circuit associated with the audio data processor to transfer the first and second audio data from the first and second locations in the I/O memory to the audio data processor for concurrent processing and output to one or more audio destinations.

2. A vehicle computer system as recited in claim 1, wherein the first audio data is output to a first set of speakers and the second audio data is simultaneously output to a second set of speakers.

3. A vehicle computer system as recited in claim 1, further comprising a synchronization circuit to synchronize a first rate at which the first memory access circuit transfers the first audio data from the first data source to the first location in the I/O memory with a second rate at which the third memory access circuit reads the first audio data from the first location in the I/O memory.

4. A vehicle computer system as recited in claim 1, wherein the first memory access circuit and the second memory access circuit are configured to write audio data to a ping buffer in the I/O memory while the third memory access circuit reads previously written audio data from a pong buffer in the I/O memory.

5. A vehicle computer system as recited in claim 4, further comprising a master clock adjuster circuit configured to monitor a first rate at which the audio data is written by the first and second memory access circuits to the ping buffer and adjust a reference audio clock associated with the third memory access circuit reading the previously written audio data from the pong buffer at a second rate such that the first rate is equal to the second rate.

6. A vehicle computer system as recited in claim 1, wherein the first data source includes one or more of:

a security system;

a navigation system;

a CD-ROM changer;

a television tuner.

7. A vehicle computer system as recited in claim 1, wherein the second data source includes one or more of:

a security system;

a navigation system;

a CD-ROM changer;

a television tuner.

8. A vehicle computer system as recited in claim 1, further comprising a master audio clock signal for use throughout the vehicle computer system system.

9. A vehicle computer system comprising:

an AM/FM tuner module

a data memory including one or more ping/pong buffers;

an audio data processor; and

a logic unit configured to receive audio data from the AM/FM tuner module and one or more peripheral audio sources, the logic unit including an audio source direct memory access (DMA) circuit associated with the AM/FM tuner module and one or more other audio source DMA circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the audio data processor,

wherein each audio source DMA circuit is configured to;

write audio data to a ping buffer within the data memory, while the at least one data processor DMA circuit reads audio data from a pong buffer within the data memory.

10. A vehicle computer system as recited in claim 9, wherein the at least one data processor DMA circuit transfers the audio data read from the pong buffer to the audio data processor for concurrent processing and output to one or more audio destinations.

11. A vehicle computer system as recited in claim 9, further comprising a synchronization circuit to synchronize a first rate at which each audio source DMA circuit writes the audio data to the ping buffer with a second rate at which the at least one data processor DMA circuit reads the audio data from the pong buffer.

12. A vehicle computer system as recited in claim 9, further comprising a master clock adjuster circuit configured to monitor a first rate at which each audio source DMA circuit writes audio data to the ping buffer and adjust a reference audio clock associated with the at least one data processor DMA circuit reading previously written audio data from the pong buffer at a second rate such that the first rate is equal to the second rate.

13. A vehicle computer system as recited in claim 9, wherein the one or more peripheral audio sources include one or more of:

a security system;

a navigation system;

a CD-ROM changer;

a television tuner.

14. A vehicle computer system as recited in claim 9, further comprising a master audio clock signal for use throughout the vehicle computer system.

15. A vehicle computer system comprising:

a data memory including one or more ping/pong buffers;

a digital signal processor; and

a logic unit configured to receive audio data from one or more peripheral audio sources, the logic unit including one or more audio source direct memory access (DMA) circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the digital signal processor,

wherein each audio source DMA circuit is configured to;

write audio data to a ping buffer within the data memory;

and wherein the at least one data processor DMA circuit is configured to;

read audio data written by two or more audio source DMA circuits from a pong buffer within the data memory and transfer the audio data written by the two or more audio source DMA circuits to the digital signal processor for concurrent processing.

16. A vehicle computer system as recited in claim 15, wherein a audio data written by a first audio source DMA circuit to a ping pong buffer is output to a first set of speakers and audio data written by a second audio source DMA circuit to the ping pong buffer is simultaneously output to a second set of speakers.

17. A vehicle computer system as recited in claim 15, wherein the audio source DMA circuits are configured to write audio data to the ping buffer while the data processor DMA circuit reads previously written audio data from the pong buffer.

18. A vehicle computer system as recited in claim 15, wherein the one or more peripheral audio sources include one or more of:

a security system;

a navigation system;

a CD-ROM changer;

a television tuner.

19. A vehicle computer system as recited in claim 15, further comprising a master audio clock signal for use throughout the vehicle computer system system.