Energy efficient processing device

• US 20090228686A1
• Filed: 05/22/2007
• Published: 09/10/2009
• Est. Priority Date: 05/22/2007
• Status: Abandoned Application

• Current Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Koenck, Steven E., Gee, John K., Mass, Allen P., Russell, Jeffrey D.
• Application Number:
  US11/805,510
• Publication Number:
  US 20090228686A1
• Time in Patent Office: Days
• US Class Current: 712/32
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22

Abstract

A network processor with a high performance in computing throughput, size and power density for use in applications such as Software Defined Radio (SDR) mesh topology. The network processor uses a core architecture comprised of a programmable microcoded sequencer to implement state management and control, a data manipulation subsystem controlled by fully decoded microinstructions. To save power, the core architecture employs a fully decoded microcoded control unit, multiplexer based register select/write logic, between 10000 to 20000 gates, a power consumption of less than 10 mW.

Claims

1. A processing device, comprising:

a microprocessor comprising a control unit and a datapath unit, said control unit directing said datapath unit;

said control unit comprising a microcoded control unit comprising a control store and having a microprogram in said control store, with the microprogram comprising fully decoded microinstructions.

2. The processing device according to claim 1, further comprising:

a plurality of multiplexer-based register select/write logic operatively connected to said microprocessor.

3. The processing device according to claim 1, wherein said microprocessor is an ASIC.

4. The processing device according to claim 3, wherein said ASIC has a microarchitecture that is a non-high-speed optimized architectural simplicity architecture.

5. The processing device according to claim 2, further comprising:

a programmable microsequencer in said control unit to execute said microprogram;

memory coupled to the microprocessor that is external to said microprocessor;

said datapath unit comprising, operatively connected to one another, at least one multiport register, ALU, data and address interface for said main memory, and RAM on said microprocessor; and

a Frame Checking Sequence (FCS) Generator block operatively connected to said microprocessor to calculate CRC for any data transmitted by said microprocessor.

6. The processing device according to claim 5, wherein said microprocessor consumes less than 10 mW power operating at a frequency of 1.0 GHz.

7. A processing device, comprising:

a microprocessor comprising a control unit and a datapath unit, said control unit directing said datapath unit;

said control unit comprising microcoded control unit comprising a control store and having a microprogram in said control store, said control unit further comprising a microsequencer for executing said microprogram, wherein the microprogram includes fully decoded microinstructions.

8. The processing device according to claim 7, further comprising:

a plurality of multiplexer-based register select/write logic operatively connected to said microprocessor.

9. The processing device according to claim 7, wherein said microprocessor is an ASIC.

10. The processing device according to claim 9, wherein said ASIC has a microarchitecture that is a non-high-speed optimized architectural simplicity architecture.

11. The processing device according to claim 7, further comprising:

memory coupled to the microprocessor that is external to said microprocessor;

said datapath unit comprising, operatively connected to one another, at least one multiport register, ALU, data and address interface for said memory, and RAM on said microprocessor; and

a Frame Checking Sequence (FCS) Generator block operatively connected to said microprocessor to calculate CRC for any data transmitted by said microprocessor.

12. The processing device according to claim 11, wherein said microprocessor consumes less than 10 mW power operating at a frequency of 1.0 GHz.

13. A system for processing, comprising:

a control unit;

a datapath unit, which is directed by the control unit; and

a microprogram;

wherein the control unit includes a microcoded control unit, the control unit includes a control store for storing the microprogram, the control unit includes a microsequencer for executing the microprogram, and the microprogram comprises fully decoded instructions.

14. The system of claim 13, wherein the control unit and datapath unit are incorporated in a network processor implemented in a hand-held device.

15. The system of claim 13, wherein the control unit and the datapath unit are incorporated into a microprocessor.

16. The system of claim 13, wherein the system further comprises a plurality of multiplexer-based register select/write logic.

17. The system of claim 13, wherein the control unit and the datapath unit are incorporated into one selected from an ASIC and a Programmable Logic Device (PLD).

18. The system of claim 17, wherein the ASIC has an architecture that is a non-high-speed optimized architectural simplicity architecture.

19. The system of claim 15, further comprising:

a memory which is external to the microprocessor; and

a Frame Checking Sequence (FCS) Generator block for calculating CRC for any data transmitted by the microprocessor;

wherein the datapath unit further comprises at least one multiport register, an ALU, a data and address interface for the memory external to the microprocessor, and RAM.

20. The system of claim 15, wherein the microprocessor consumes less than 10 mW power when operating at a frequency of 1.0 GHz.