Pixel Structure Having Shielded Storage Node

• US 20090230289A1
• Filed: 05/28/2009
• Published: 09/17/2009
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: LePage, Gerald
• Granted Patent: US 8,207,485 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node.

Claims

1. A pixel comprising:

sample transistor coupled to a light detecting stage, the sample transistor comprising an inner junction region surrounding and coupled to a storage node, and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node; and

a memory capacitor coupled to the storage node.

2. The pixel of claim 1, wherein the sample transistor further comprises an outer junction region disposed around the inner junction region.

3. The pixel of claim 2, wherein the charge barrier shields the inner junction region from charges generated in the outer junction region.

4. The pixel of claim 3, wherein the outer junction region collects light generated charges generated in the inner junction region in proximity to the storage node.

5. The pixel of claim 1, further comprises a light shield that shields the inner junction region from light received by the pixel in operation.

6. The pixel of claim 5, wherein the light shield substantially does not shield the outer junction region from light received by the pixel in operation.

7. The pixel of claim 1, wherein the charge barrier forms an open ring around the inner junction region.

8. The pixel of claim 1, wherein the charge barrier forms a closed ring around the inner junction region.

9. The pixel of claim 1, wherein the pixel is a six transistor (6T) pixel.

10. The pixel of claim 1, further comprising one or more additional sample transistors having a gate disposed around an inner junction region that operates as a charge barrier.

11. A synchronous shutter image sensor comprising a plurality of the pixels of claim 1.

12. A method comprising generating an active-pixel layout including a sample transistor having an inner junction region, an outer junction region disposed around the inner junction region, and a gate charge barrier disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the inner junction region from charges generated in the outer junction region.

13. The method of claim 12, wherein generating the active-pixel layout further comprises generating the pixel layout to have a storage node surrounded by and coupled to the inner junction region.

14. The method of claim 12, wherein generating the active pixel layout comprises laying out the gate to form an open ring around the inner junction region.

15. The method of claim 12, wherein generating the active-pixel layout comprises laying out the gate to form a closed ring around the inner junction region.

16. The method of claim 12, wherein generating the active-pixel layout comprises laying out the gate to form a closed ring around the inner junction region.

17. An apparatus comprising an active-pixel sensor including a sample transistor having a storage node, an outer junction region disposed closed ring around the storage node, and means for reducing a parasitic light sensitivity (PLS) of the pixel by shielding the storage node from charges generated in the outer junction region.

18. The apparatus of claim 17, wherein the means for reducing the PLS comprises a charge barrier disposed around at least three sides of the storage node.

19. The pixel of claim 18, wherein the charge barrier operates as a gate of the sample transistor in operation of the active-pixel sensor.

20. The pixel of claim 18, wherein the charge barrier forms a closed ring around the inner junction region.