FINGER CAPACITOR STRUCTURES
First Claim
1. An Integrated Circuit (IC) finger capacitor structure comprising:
- a plurality of capacitor node conductor pairs, each of a respective metal layer and each comprising;
a first node conductor having a base portion and a plurality of finger portions;
a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor; and
dielectric horizontally disposed between the first node conductor and the second node conductor;
at least one dielectric layer vertically separating adjacent metal layers, each dielectric layer comprisingdielectric disposed between the adjacent metal layers; and
a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers; and
a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers, the plurality of first node vias and plurality of second node vias having staggered spacing to preclude laterally adjacent first node vias and second node vias.
4 Assignments
0 Petitions
Accused Products
Abstract
A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor. Dielectric is horizontally disposed between the first node conductor and the second node conductor. At least one dielectric layer vertically separates adjacent metal layers, each dielectric layer including dielectric disposed between the adjacent metal layers, a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers, and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers. The plurality of first node vias and plurality of second node vias have staggered spacing to preclude laterally adjacent first node vias and second node vias.
8 Citations
12 Claims
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1. An Integrated Circuit (IC) finger capacitor structure comprising:
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a plurality of capacitor node conductor pairs, each of a respective metal layer and each comprising; a first node conductor having a base portion and a plurality of finger portions; a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor; and dielectric horizontally disposed between the first node conductor and the second node conductor; at least one dielectric layer vertically separating adjacent metal layers, each dielectric layer comprising dielectric disposed between the adjacent metal layers; and a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers; and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers, the plurality of first node vias and plurality of second node vias having staggered spacing to preclude laterally adjacent first node vias and second node vias. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An Integrated Circuit (IC) comprising:
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communication circuitry; and a capacitor coupled to the communication circuitry and including; a plurality of capacitor node conductor pairs, each of a respective metal layer and each comprising; a first node conductor having a base portion and a plurality of finger portions; a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor; and dielectric horizontally disposed between the first node conductor and the second node conductor; at least one dielectric layer vertically separating adjacent metal layers, each dielectric layer comprising dielectric disposed between the adjacent metal layers; and a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers; and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers, the plurality of first node vias and plurality of second node vias having staggered spacing to preclude laterally adjacent first node vias and second node vias. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification