DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT

• US 20090230994A1
• Filed: 03/11/2009
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Byung-Koan, Rhee, Young-Chul, Shin, Ock-Chul
• Granted Patent: US 7,852,121 B2
• Time in Patent Office: Days
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Claims

1. A domino logic circuit comprising:

an input circuit configured to precharge a dynamic node at a first phase of a clock signal and configured to determine a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and

an output circuit coupled between an output node and the dynamic node, the output circuit being configured to determine a logic level of the output node in response to the clock signal and the logic level of the dynamic node and to maintain the logic level of the output node while the logic evaluation is performed.

2. The domino logic circuit of claim 1, wherein the input circuit includes:

a precharge transistor configured to precharge the dynamic node at the first phase of the clock signal;

a logic network configured to receive the input data to determine the logic level of the dynamic node in response to a logic level of the input data; and

a pull down transistor configured to enable or disable the logic network in response to the clock signal.

3. The domino logic circuit of claim 2, wherein the precharge transistor comprises a PMOS transistor having a source terminal coupled to a power supply voltage, a drain terminal coupled to the dynamic node, and a gate terminal receiving the clock signal, and

wherein the pull down transistor comprises an NMOS transistor having a source terminal coupled to a ground voltage, a drain terminal coupled to the logic network, and a gate terminal receiving the clock signal.

4. The domino logic circuit of claim 3, wherein the logic network includes a plurality of transistors serially coupled to form a current path between the dynamic node and the pull down transistor, the plurality of the transistors having control terminals receiving the input data.

5. The domino logic circuit of claim 3, wherein the logic network includes a plurality of transistors coupled in parallel to form a plurality of current paths between the dynamic node and the pull down transistor, the plurality of the transistors having control terminals receiving the input data.

6. The domino logic circuit of claim 1, wherein the output circuit includes:

a cut-off transistor coupled between the dynamic node and an intermediate node, the cut-off transistor being configured to disconnect the dynamic node and the intermediate node at the first phase of the clock signal; and

an output maintaining circuit configured to maintain the logic level of the output node during a phase transition of the clock signal.

7. The domino logic circuit of claim 6, wherein the cut-off transistor has a first terminal coupled to the dynamic node, a second terminal coupled to the intermediate node, and a gate terminal receiving the clock signal.

8. The domino logic circuit of claim 7, wherein the output maintaining circuit includes:

a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to the output node;

a second transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node;

a third transistor having a first terminal coupled to the output node, a second terminal coupled to a ground voltage, and a gate terminal coupled to the intermediate node; and

a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node.

9. A domino logic circuit comprising:

a precharge transistor configured to precharge a dynamic node at the first phase of a clock signal;

a logic network coupled to the dynamic node, the logic network being configured to determine a logic level of the dynamic node by performing a logic evaluation of input data;

a pull down transistor coupled between the logic network and a ground voltage to receive the clock signal;

a cut-off transistor having a first terminal coupled to the dynamic node, a second terminal coupled to the intermediate node, and a gate terminal receiving the clock signal;

a first transistor having a first terminal coupled to a power supply voltage, a second terminal coupled to the intermediate node, and a gate terminal coupled to an output node;

a second transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the dynamic node;

a third transistor having a first terminal coupled to the output node, a second terminal coupled to the ground voltage, and a gate terminal coupled to the intermediate node; and

a fourth transistor having a first terminal coupled to the power supply voltage, a second terminal coupled to the output node, and a gate terminal coupled to the intermediate node.

10. The domino logic circuit of claim 9, wherein a logic level of the output node is maintained while the logic evaluation of the input data is performed.

11. A pipelined domino logic circuit comprising:

a first logic block configured to perform a logic evaluation of first input data in response to a clock signal and configured to generate a first output signal, a logic level of the first output signal being maintained while the logic evaluation is performed; and

a second logic block configured to perform a logic evaluation of second input data in response to the clock signal, the second input data including the first output signal, the second logic block being configured to generate a second output signal, a logic level of the second output signal being maintained while the logic evaluation is performed.

12. The pipelined domino logic circuit of claim 11, wherein the first logic block includes:

a first input circuit configured to precharge a first dynamic node at a first phase of the clock signal and configured to determine a logic level of the first dynamic node by performing a logic evaluation of input data at a second phase of the clock signal; and

a first output circuit coupled between a first output node and the first dynamic node, the first output circuit being configured to generate the first output signal in response to the clock signal and the logic level of the first dynamic node.

13. The pipelined domino logic circuit of claim 12, wherein the second logic block includes:

a second input circuit configured to precharge a second dynamic node at the first phase of the clock signal and configured to determine a logic level of the second dynamic node by performing a logic evaluation of the second input data at the second phase of the clock signal; and

a second output circuit coupled between a second output node and the second dynamic node, the second output circuit being configured to generate the second output signal in response to the clock signal and the logic level of the second dynamic node.

14. The pipelined domino logic of claim 13, wherein the first input circuit includes:

a first precharge transistor configured to precharge the first dynamic node at the first phase of the clock signal;

a first logic network configured to receive the first input data to determine the logic level of the first dynamic node in response to a logic level of the first input data; and

a first pull down transistor configured to enable or disable the first logic network in response to the clock signal.

15. The pipelined domino logic of claim 14, wherein the first output circuit includes:

a first cut-off transistor coupled between the first dynamic node and a first intermediate node, the first cut-off transistor being configured to disconnect the first dynamic node and the first intermediate node at the first phase of the clock signal; and

a first output maintaining circuit configured to maintain a logic level of the first output node during a phase transition of the clock signal.

16. The domino logic circuit of claim 14, wherein the second input circuit includes:

a second precharge transistor configured to precharge the second dynamic node at the first phase of the clock signal;

a second logic network configured to receive the second input data to determine the logic level of the second dynamic node in response to a logic level of the second input data; and

a second pull down transistor configured to enable or disable the second logic network in response to the clock signal.

17. The pipelined domino logic circuit of claim 16, wherein the second output circuit includes:

a second cut-off transistor coupled between the second dynamic node and a second intermediate node, the second cut-off transistor being configured to disconnect the second dynamic node and the second intermediate node at the first phase of the clock signal; and

a second output maintaining circuit configured to maintain a logic level of the second output node during a phase transition of the clock signal.

18. A pipelined domino logic circuit comprising a plurality of logic blocks sequentially connected, each logic block comprising:

an input circuit configured to precharge a dynamic node of the each logic block at a first phase of a clock signal, the input circuit being configured to determine a logic level of the dynamic node of the each logic block by performing a logic evaluation of input data of the each logic block at a second phase of the clock signal, the input data of the each logic block including an output signal of a previous logic block; and

an output circuit coupled between an output node of the each logic block and the dynamic node of the each logic block, the output circuit being configured to determine an output signal of the each logic block in response to the clock signal and the logic level of the dynamic node of the each logic block, and provide the output signal of the each logic block to a next logic block, the output circuit being configured to maintain a logic level of the output signal of the each logic block while the logic evaluation is performed.

19. The pipelined domino logic circuit of claim 19, wherein the input circuit includes:

a precharge transistor configured to precharge the dynamic node of the each logic block at the first phase of the clock signal;

a logic network configured to determine the logic level of the dynamic node of the each logic block in response to a logic level of the input data of the each logic block; and

a pull down transistor configured to enable or disable the logic network in response to the clock signal.

20. The pipelined domino logic circuit of claim 19, wherein the output circuit includes:

a cut-off transistor coupled between the dynamic node and a intermediate node, the cut-off transistor being configured to disconnect the dynamic node and the intermediate node at the first phase of the clock signal; and

an output maintaining circuit configured to maintain a logic level of the output signal of the each logic block during a phase transition of the clock signal.