PROCESS TO MAKE METAL OXIDE THIN FILM TRANSISTOR ARRAY WITH ETCH STOPPING LAYER

• US 20090236597A1
• Filed: 03/17/2009
• Published: 09/24/2009
• Est. Priority Date: 03/20/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: YE, YAN
• Granted Patent: US 8,143,093 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.

Claims

1. A thin film transistor formation method, comprising:

depositing and patterning a gate electrode over a substrate;

depositing a gate dielectric layer over the gate electrode;

depositing a semiconductive active layer over the gate dielectric layer, the semiconductive active layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, indium, cadmium, gallium, and tin;

depositing an etch stop layer over the active layer;

forming a first mask over the etch stop layer;

etching the etch stop layer to form a patterned etch stop layer;

removing the first mask to expose the patterned etch stop layer;

depositing a metal layer over the patterned etch stop layer;

forming a second mask over the metal layer;

etching the metal layer to define a source electrode and a drain electrode;

removing the second mask;

etching the active layer using the source electrode and the drain electrode as a mask; and

depositing a passivation layer over the source electrode and the drain electrode.

2. The method of claim 1, wherein etching the metal layer comprises plasma etching and wherein etching the active layer comprises wet etching.

3. The method of claim 2, wherein etching the active layer comprises utilizing the source electrode, the drain electrode and the patterned etch stop layer collectively as a mask without depositing and removing an additional mask.

4. The method of claim 1, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxide and combinations thereof.

5. The method of claim 1, wherein the etch stop layer is deposited by plasma enhanced chemical vapor deposition.

6. The method of claim 5, wherein the active layer is deposited by applying a DC electrical bias to a metallic sputtering target comprising the one or more elements selected from the group consisting of zinc, indium, cadmium, gallium, and tin, and introducing an oxygen containing gas and a nitrogen containing gas.

7. The method of claim 6, wherein the oxygen containing gas and the nitrogen containing gas are separate gases.

8. The method of claim 7, wherein the sputtering target comprises a dopant selected from the group consisting of Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, SiC, and combinations thereof.

9. The method of claim 1, wherein the active layer comprises a dopant selected from the group consisting of Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, SiC, and combinations thereof.

10. A method, comprising:

depositing a semiconductor layer over a substrate, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, and tin;

depositing an etch stop layer over the semiconductor layer;

forming a first mask over the etch stop layer;

patterning the etch stop layer to form a patterned etch stop layer;

removing the first mask;

depositing a metal layer over the patterned etch stop layer and the semiconductor layer;

forming a second mask over the metal layer;

etching the metal layer to form a patterned metal layer;

removing the second mask; and

etching at least a portion of the semiconductor layer while using the patterned metal layer and the patterned etch stop layer as masks.

11. The method of claim 10, wherein the etching the metal layer comprises plasma etching and wherein the etching the semiconductor layer comprises wet etching.

12. The method of claim 10, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxide and combinations thereof.

13. The method of claim 10, wherein the etch stop layer is deposited by plasma enhanced chemical vapor deposition.

14. The method of claim 10, wherein the semiconductor layer is deposited by applying a DC electrical bias to a sputtering target comprising the one or more elements selected from the group consisting of zinc, indium, cadmium, gallium, and tin, and introducing an oxygen containing gas and a nitrogen containing gas.

15. The method of claim 14, wherein the oxygen containing gas and the nitrogen containing gas are separate gases.

16. The method of claim 15, wherein the sputtering target comprises a dopant selected from the group consisting of Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, SiC, and combinations thereof.

17. The method of claim 10, wherein the semiconductor layer comprises a dopant selected from the group consisting of Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, SiC, and combinations thereof.

18. A thin film transistor, comprising:

a gate electrode disposed over a substrate;

a gate dielectric layer disposed over the gate electrode;

a semiconductor layer disposed over the gate dielectric layer, the semiconductor layer comprising oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, gallium, indium, cadmium, and tin;

a source electrode;

a drain electrode; and

an etch stop layer disposed over the semiconductor layer and between the source electrode and the drain electrode.

19. The thin film transistor of claim 18, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxide and combinations thereof.

20. The thin film transistor of claim 18, wherein the semiconductor layer comprises a dopant selected from the group consisting of Al, Sn, Ga, Ca, Si, Ti, Cu, Ge, In, Ni, Mn, Cr, V, Mg, Si_xN_y, Al_xO_y, SiC, and combinations thereof.