SYSTEMS AND DEVICES INCLUDING MULTI-TRANSISTOR CELLS AND METHODS OF USING, MAKING, AND OPERATING THE SAME

• US 20090238010A1
• Filed: 03/20/2008
• Published: 09/24/2009
• Est. Priority Date: 03/20/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 8,546,876 B2
• Time in Patent Office: Days
• US Class Current: 365/189.70
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain.

Claims

1. A device, comprising:

a plurality of data cells, wherein each data cell comprises;

a first transistor comprising;

a column gate; and

a first channel;

a second transistor comprising;

a row gate, wherein the row gate crosses over the column gate, under the column gate, or both;

a source disposed near a distal end of a first leg;

a drain disposed near a distal end of a second leg, wherein the column gate extends between the first leg and the second leg;

a second channel, wherein the second channel of the second transistor is connected to the first channel of the first transistor; and

a data element connected to the source or the drain.

2. The device of claim 1, wherein the data element comprises a memory element or an imaging element.

3. The device of claim 1, wherein the second channel of the second transistor comprises a pair of channels connected by the first channel of the first transistor.

4. A device, comprising:

stacked upper and lower transistors, wherein the channel of the upper transistor overlaps the channel of the lower transistor.

5. The device of claim 4, wherein a portion of the channel of the upper transistor is generally perpendicular to a portion of the channel of the lower transistor.

6. The device of claim 4, wherein the stacked upper and lower transistors comprise a first leg with a doped distal portion and a second leg with a doped distal portion, and wherein the doped distal portion of the second leg is longer than the doped distal portion of the first leg and connects to the channel of the lower transistor.

7. The device of claim 4, wherein a portion of the channel of the upper transistor is generally vertical.

8. The device of claim 4, wherein the upper transistor and the lower transistor form an AND gate.

9. The device of claim 4, wherein the upper transistor and the lower transistor form an OR gate.

10. The device of claim 4, wherein a gate of the upper transistor is generally perpendicular to a gate of the lower transistor.

11. The device of claim 4, wherein the lower transistor comprises two gates.

12. The device of claim 4, wherein the upper transistor comprises two gates.

13. The device of claim 4, wherein the upper transistor comprises a pair of legs.

14. The device of claim 13, wherein the lower transistor comprises a gate extending between the pair of legs.

15. The device of claim 14, wherein the upper transistor comprises a pair of gates disposed on either side of the pair of legs.

16. The device of claim 15, wherein the pair of legs each comprise a distal portion that is doped different from a lower portion.

17. An apparatus, comprising:

an array of data cells, each data cell comprising a pair of transistors;

a select-line driver connected to the one of the transistors in the pair of transistors in each data cell; and

a sense amplifier connected to a first group of data cells in the array by a first data line and a second group of data cells in the array by a second data line, wherein the select-line driver is configured to disable the first group when the sense amplifier reads data from the second group.

18. The apparatus of claim 17, wherein the select-line driver is configured to disable the second group when the sense amplifier reads data from the first group.

19. The apparatus of claim 17, wherein the pair of transistors comprise a pair of transistors with generally orthogonal gates.

20. The apparatus of claim 17, wherein the sense amplifier is configured to read data by comparing a voltage of the first digit to a voltage of the second data line.

21. The apparatus of claim 17, wherein each data cell comprises a capacitor plate.

22. A method of reading data, comprising:

turning on a first group of transistors including a first transistor connected to a first data element being read;

turning off or leaving off a second group of transistors while the first group of transistors is turned on;

turning on a second transistor connected to the first data element being read and not in the first group of transistors;

conducting a current between the first data element being read and a first data line, wherein the current is conducted through the first transistor and the second transistor; and

comparing a signal from the first data line connected to the first data element to a signal from a second data line connected to the second group of transistors.

23. The method of claim 22, wherein conducting the current through the first transistor and the second transistor comprises conducting the current through the first transistor, then through the second transistor, then through the first transistor again.

24. The method of claim 22, wherein comparing the signal from the first data line connected to the first data element to a signal from a second data line connected to the second group of transistors comprises determining whether a voltage of the first data line connected to the first data element is larger than a voltage of the second data line connected to the second group of transistors.

25. The method of claim 22, comprising:

turning on the second group of transistors including a third transistor connected to a second data element being read;

turning off or leaving off the first group of transistors while the second group of transistors is turned on;

turning on a fourth transistor connected to the second data element being read and not in the second group of transistors;

conducting a second current between the second data element being read and the second data line, wherein the second current is conducted through the third transistor and the fourth transistor; and

comparing a signal from the second data line connected to the second data element to a signal from the first data line connected to the first group of transistors.

26. A method, comprising:

applying a voltage across a source and a drain of a tri-gate transistor, wherein the tri-gate transistor comprises a fin field-effect transistor having a first gate, a second gate, and a third gate.

27. The method of claim 26, comprising:

applying a first voltage to the first gate and a second voltage to the second gate, wherein the first voltage and the second voltage are different voltages; and

conducting a current through a channel of the tri-gate transistor adjacent the first gate and not through another channel of the tri-gate transistor adjacent the second gate.

28. A method, comprising:

forming a first gate in a trench;

forming a row of fins extending generally perpendicular to the first gate; and

forming a second gate that crosses over the first gate.

29. A method, comprising:

forming a pair of isolation trenches in a substrate;

forming a first gate disposed between the pair of isolation trenches;

forming a second gate overlapping the first gate and the pair of isolation trenches.

30. A method, comprising:

forming a pair of legs extending from a substrate;

forming a first gate that disposed between the pair of legs; and

forming a second gate disposed adjacent both legs in the pair of legs.