PROCESS VARIATION BASED MICROCHIP IDENTIFICATION

• US 20090243792A1
• Filed: 03/31/2008
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Chmelar, Erik V.
• Granted Patent: US 8,432,250 B2
• Time in Patent Office: Days
• US Class Current: 340/5.600
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.

Claims

1. An apparatus comprising:

a multiplexer circuit configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal;

a plurality of bit generation circuits each configured to generate one of said plurality of input bits; and

a control circuit configured to generate said control signal.

2. The apparatus according to claim 1, wherein said apparatus generates said intermediate signal within a tolerance needed to be used as an encryption key.

3. The apparatus according to claim 1, wherein each of said bit generation circuits generates one of said input bits in response to (i) a first transistor signal, (ii) a second transistor signal, and (iii) a pinch signal.

4. The apparatus according to claim 3, wherein said first and second transistor signals are generated in response to two or more transistors used to implement various components of said apparatus.

5. The apparatus according to claim 1, further comprising:

a decision circuit configured to generate a second intermediate signal in response to said first intermediate signal.

6. The apparatus according to claim 5, further comprising:

a memory circuit configured to receive said second intermediate signal.

7. The apparatus according to claim 5, wherein said control circuit generates said control signal in response to a mode signal, wherein said mode signal is configured to control whether said decision circuit generates (i) said intermediate signal when in a first mode and (ii) one or more counter signals configured to indicate a degree of accuracy of said apparatus when in a second mode.

8. The apparatus according to claim 1, wherein said intermediate signal comprises a multi-bit signal.

9. The apparatus according to claim 1, wherein said control circuit generates said control signal in response to a mask signal, wherein said mask signal is configured to select which of said plurality of bits is used to generate said intermediate signal.

10. A method for generating a chip identification, comprising the steps of:

(A) generating an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal;

(B) generating a plurality of input bits in response to a plurality of bit generation circuits; and

(C) generating said control signal.

11. The method according to claim 10, wherein step (A) generates said intermediate signal within a tolerance needed to be used as an encryption key.

12. The method according to claim 10, wherein each of said bit generation circuits generates one of said input bits in response to (i) a first transistor signal, (ii) a second transistor signal, and (iii) a pinch signal.

13. The method according to claim 12, wherein said first and second transistor signals are generated in response to two or more transistors used to implement various components of said method.

14. The method according to claim 10, further comprising:

a decision circuit configured to generate a second intermediate signal in response to said first intermediate signal.

15. The method according to claim 14, further comprising:

receiving said second intermediate signal by a memory circuit.

16. The method according to claim 10, wherein said intermediate signal comprises a multi-bit signal.

17. A method for generating a bit pattern, comprising the steps of:

(A) generating a plurality of bits;

(B) generating a first count value indicating a number of times a first digital value is generated within said plurality of bits;

(C) generating a second count value indicating a number of times a second digital value is generated within said plurality of bits;

(D) if said first count value and said second count value are within a predetermined tolerance, storing said bit pattern; and

(E) repeating steps (A) through (D) if said first count value and said second count value are not within a predetermined tolerance.

18. The method according to claim 17, wherein said predetermined tolerance is sufficient to use said bit pattern as an encryption key.