MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL

• US 20090248957A1
• Filed: 03/31/2008
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Tzeng, Tzungren Allan
• Granted Patent: US 8,560,761 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.

Claims

1. An operating system, comprising:

a virtual management component that manages one or more FLASH memory devices separately from other system resources associated with the devices; and

a buffer component that operates in conjunction with the virtual management component to account for latencies to the one or more FLASH devices.

2. The system of claim 1, further comprising a free list component associated with the FLASH memory devices.

3. The system of claim 2, further comprising a cache list component associated with the FLASH memory devices.

4. The system of claim 1, further comprising a free list component associated with the buffer component.

5. The system of claim 4, further comprising a cache list component associated with the buffer component.

6. The system of claim 1, further comprising a component to detect when memory pages have been freed.

7. The system of claim 6, the component detects when pages have been mapped to a virtual address and to a swap file system.

8. The system of claim 6, the component detects when pages have been mapped to a virtual address and to a File.

9. The system of claim 6, the pages are allocated based on whether or not hits are detected to an existing mapped page.

10. The system of claim 6, the pages are allocated based off of page faults that include major faults, minor faults, or protection faults.

11. The system of claim 6, further comprising a read page fault that triggers a page-in operation permanent storage.

12. The system of claim 11, further comprising a page scanner that frees one or more pages to one or more lists.

13. The system of claim 12, the page scanner is triggered from a FLASH memory shortage or a buffer memory shortage.

14. The system of claim 13, the buffer component is adapted to a dynamic data ram (DDR) memory channel.

15. The system of claim 13, further comprising a minor page fault that triggers a mapping to an existing physical page.

16. The system of claim 15, further comprising a configuration option to allocate a DRAM page directly upon a read page fault.

17. The system of claim 16, the configuration option allows moving pages during background operations.

19. The method of claim 17, further comprising moving data to the FLASH memory devices during background memory operations.

18. A method to operate a memory subsystem, comprising:

managing a free list and a cache list for one or more FLASH memory devices; and

managing a free list and a cache list for one or more DRAM memory devices, where the lists are managed by an operating system.

20. An operating system, comprising:

means for controlling a free list and a cache list for one or more FLASH memory devices; and

means for controlling a free list and a cache list for one or more DRAM memory devices, where the lists are concurrently managed by a single operating system.