METHOD AND APPARATUS FOR DYNAMIC POWER MANAGEMENT CONTROL USING SERIAL BUS MANAGEMENT PROTOCOLS

• US 20090249089A1
• Filed: 03/26/2009
• Published: 10/01/2009
• Est. Priority Date: 03/28/2008
• Status: Active Grant

• Current Assignee: Packet Digital, LLC
• Original Assignee: Packet Digital, LLC
• Inventors: Tremel, Christopher J., Schmitz, Michael J., Morlock, Brian M.
• Granted Patent: US 8,312,299 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for on-demand power management includes an I/O serial communication master device, peripheral devices that communicate with the master device along the serial bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to minimize energy consumption and reduce system latency.

Claims

1. A computer-implemented method, comprising:

providing a first operating voltage and a first clock frequency to a peripheral device, operating in a first operating state, wherein the peripheral device is coupled to an input-output (I/O) controller in a processing system with a serial bus;

monitoring bus transactions on the serial bus using a power manager, coupled between the I/O controller and the peripheral device, to assess a current processing demand for the peripheral device; and

dynamically adjusting at least one of the first operating voltage or the first clock frequency in response to the current processing demand.

2. The method of claim 1, wherein monitoring comprises:

receiving at the power manager a current bus transaction from the I/O controller; and

determining whether the peripheral device is to operate in a second operating state to process the current bus transaction, wherein the second operating state corresponds to the current processing demand, and wherein dynamically adjusting comprises switching the peripheral device to operate in the second operating state to allow the peripheral device to process the current bus transaction, wherein the first operating state is a lower power state than the second operating state.

3. The method of claim 1, wherein dynamically adjusting comprises:

adjusting the first operating voltage to a second operating voltage; and

adjusting the first clock frequency to a second clock frequency.

4. The method of claim 3, wherein adjusting the second clock frequency comprises:

generating the second clock frequency in response to the current processing demand, wherein the second clock frequency is phase-locked to a reference frequency and phase-matched to the first clock frequency; and

switching from the first clock frequency to the second clock frequency without halting the processing system.

5. The method of claim 1, wherein dynamically adjusting comprises adjusting the first operating voltage to a second operating voltage.

6. The method of claim 1, wherein dynamically adjusting comprises adjusting the first clock frequency to a second clock frequency.

7. The method of claim 2, further comprising delaying the current bus transaction from being sent to the peripheral device using the power manager, wherein the current bus transaction is delayed until the power manager finishes the adjusting.

8. The method of claim 7, wherein delaying the current bus transaction comprises:

storing the current bus transaction in a buffer; and

transmitting the current bus transaction to the peripheral device when the power manager finishes the adjusting.

9. The method of claim 7, wherein delaying the current bus transaction comprises notifying the I/O controller that the peripheral device is busy to pause the current bus transaction from the I/O controller.

10. The method of claim 7, wherein delaying the current bus transaction comprises stretching a clock signal between the I/O controller and the power manager to place the I/O controller in a wait state for the current bus transaction.

11. The method of claim 10, wherein the current bus transaction is an inter-integrated circuit (I2C) transaction, and wherein stretching the clock signal comprises holding the clock line between the power manager and the I/O controller low until the power manager finishes the adjusting to pause the I2C transaction from the I/O controller.

12. The method of claim 1, wherein a plurality of peripheral devices are coupled to the I/O controller using the power manager, including the peripheral device, and wherein the monitoring comprises:

receiving a start signal from the I/O controller for a current bus transaction;

decoding a device address of the current bus transaction to select one of the plurality of peripheral devices to send the current bus transaction;

delaying the current bus transaction from being sent to the selected peripheral device by placing the I/O controller in a wait state for the current bus transaction;

while delaying the current bus transaction, transitioning the selected peripheral device to a second operating state from the first operating state by said dynamically adjusting, wherein the first operating state is a lower power state than the second operating state; and

initiating a device communication flow between the I/O controller and the peripheral device for the current bus transaction when the selected peripheral device is operating at the second operating state.

13. The method of claim 12, wherein the monitoring further comprises transitioning the selected peripheral device to the first operating state from the second operating state when the current bus transaction is completed.

14. The method of claim 12, wherein the monitoring further comprises determining that the selected peripheral device is an I2C device, and wherein initiating the device communication flow comprises:

sending the start signal to the I2C device;

releasing the clock line between the I/O controller and the power manager; and

buffering data and clock lines between the I/O controller and the I2C device.

15. The method of claim 12, wherein the monitoring further comprises determining that the selected peripheral device is a serial peripheral interface (SPI) device, and wherein initiating the device communication flow comprises:

asserting a chip select (CS) signal to the SPI device;

releasing the clock line between the I/O controller and the power manager to activate the I/O controller from the wait state; and

determining whether the current bus transaction is a read operation or a write operation, wherein if the current bus transaction is a read operation, the determining comprises;

holding the clock line between the I/O controller and the power manager low;

reading a first set of one or more bits of data from SPI device;

releasing the clock line between the I/O controller and the power manager; and

sending the first set of data to the I/O controller, and

wherein if the current bus transaction is a write operation, the determining comprises;

buffering a second set of one or more bits of data received from the I/O controller;

acknowledging the I/O controller;

holding the clock line between the I/O controller and the power manager low;

sending the second set of data received from the I/O controller to the SPI device; and

releasing the clock line between the I/O controller and the power manager.

16. The method of claim 12, wherein the monitoring further comprises determining that the selected peripheral device is a universal asynchronous receiver and transceiver (UART) device, and wherein initiating the device communication flow comprises determining whether the current bus transaction is a read operation or a write operation,

wherein if the current bus transaction is a read operation, the determining comprises:

holding the clock line between the I/O controller and the power manager low;

reading a first set of one or more bits of data from a buffer of the UART device;

releasing the clock line between the I/O controller and the power manager; and

sending the first set of data to the I/O controller, and

wherein if the current bus transaction is a write operation, the determining comprises;

buffering a second set of one or more bits of data received from the I/O controller;

acknowledging the I/O controller;

holding the clock line between the I/O controller and the power manager low;

sending the second set of data received from the I/O controller to the UART device; and

releasing the clock line between the I/O controller and the power manager.

17. An apparatus, comprising:

a first bus interface coupled to an input-output (I/O) controller to communicate bus transactions of a serial bus between the I/O controller and a peripheral device in a processing system;

a second bus interface coupled to the peripheral device to communicate the bus transactions of the serial bus between the I/O controller and the peripheral device, wherein the first peripheral device is operated at a first operating state; and

a monitoring engine coupled to the first and second bus interfaces to monitor the bus transactions on the serial bus to assess a current processing demand for the peripheral device, and to dynamically adjust at least one of a first operating voltage or a first clock frequency, supplied to the peripheral device in the first operating state, in response to the current processing demand.

18. The apparatus of claim 17, wherein the monitoring engine is configured to receive a current bus transaction from the I/O controller, to determine whether the peripheral device is to operate in a second operating state for the current bus transaction, and to switch the peripheral device to operate in the second operating to allow the peripheral device to process the current bus transaction, wherein the first operating state is a lower power state than the second operating state.

19. The apparatus of claim 18, further comprising an adjustable voltage regulator coupled to receive a signal from the monitoring engine to adjust the first operating voltage supplied to the peripheral device to a second operating voltage when the monitoring engine switches the peripheral device to the second operating state.

20. The apparatus of claim 18, further comprising a multiplexer coupled to the monitoring engine to adjust the first clock frequency to a second clock frequency when the monitoring engine switches the peripheral device to the second operating state.

21. The apparatus of claim 18, further comprising a converter coupled between the monitoring engine and the second bus interface to translate a first bus protocol of the current bus transaction, used by the I/O controller, to a second bus protocol, used by the peripheral device.

22. A computer-implemented method, comprising:

buffering bus transactions on a serial bus between a plurality of peripheral devices and a host processing device in a processing system using a power manager;

monitoring the bus transactions on the serial bus to assess a current processing demand for at least one of a plurality of peripheral devices, wherein the current processing demand correlates to an operating state of the at least one peripheral device; and

compensating for the current processing demand by dynamically scaling at least one of an operating voltage or a clock frequency supplied to the at least one peripheral device to meet the current processing demand.

23. The method of claim 22, wherein the at least one peripheral device is operating at a first clock frequency, and wherein dynamically scaling the clock frequency supplied to the at least one peripheral device comprises:

generating a second clock frequency in response to the current processing demand, wherein the second clock frequency is phase-matched to the first clock frequency; and

switching from the first clock frequency to the second clock frequency without halting the processing system.

24. The method of claim 22, wherein the at least one peripheral device is operating at a first voltage, and wherein dynamically scaling the operating voltage supplied to the at least one peripheral device comprises:

generating a second voltage in response to the current processing demand; and

switching from the first voltage to the second voltage without halting the processing system.