SEMICONDUCTOR MEMORY HAVING VOLATILE AND MULTI-BIT, NON-VOLATILE FUNCTIONALITY AND METHODS OF OPERATING

• US 20090251966A1
• Filed: 04/08/2009
• Published: 10/08/2009
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 8,014,200 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Claims

1. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;

a trapping layer positioned in between the first and second locations and above a surface of the substrate;

the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and

a control gate positioned above the trapping layer.

2. The semiconductor memory cell of claim 1, wherein said first and second storage locations are each configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the trapping layer.

3. The semiconductor memory cell of claim 2, wherein only one of said first and second storage locations is configured to receive transfer of data stored by the volatile memory upon interruption of power to the memory cell.

4. The semiconductor memory cell of claim 1, wherein the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type.

5. The semiconductor memory cell of claim 4, wherein said floating body is completely bounded by said top surface, said first and second regions and said buried layer.

6. The semiconductor memory cell of claim 1, wherein the first conductivity type is “

p”

type and the second conductivity type is “

n”

type.

7. The semiconductor memory cell of claim 1, further comprising insulating layers bounding the side surfaces of the substrate.

8. The semiconductor memory cell of claim 1, wherein said cell is configured for use as non-volatile memory with fast read/write speed, and wherein said volatile memory is used as a write buffer.

9. The semiconductor memory cell of claim 1, wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body.

10. The semiconductor memory cell of claim 1, wherein said cell functions as a multi-level cell.

11. The semiconductor memory cell of claim 10, wherein at least one of said first and second storage locations is configured so that more than one bit of data can be stored in said at least one of said first and second storage locations, respectively.

13. The method of claim 12, wherein said cells are arranged in rows and columns, and wherein, after a plurality of cells have stored a bit of volatile data, each in the floating body of each said cell, respectively, and after the volatile data has been written to the nonvolatile storage by storing in one of two storage locations provided in a trapping layer of each said cell, respectively, said method further comprising repeating the steps of claim 10, but wherein said writing of data from said floating bodies to said non-volatile memory comprises storing said data in said second location of said trapping layer of said cell, respectively for the plurality of cells.

12. A method of operating a memory cell device having a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a trapping layer having first and second storage locations for storing data as non-volatile memory, the method comprising:

writing data to the floating body of a memory cell of said device;

writing additional data to the floating body of another memory cell of said device, while at the same time commencing writing data from the floating body of the previous memory cell to non-volatile storage of that cell; and

continuing to write additional data to the floating bodies of more memory cells of said device, as volatile memory, while at the same time, writing volatile memory from cells in which data has already been written to the floating bodies thereof, to non-volatile memory in a mass parallel, non-algorithmic process.

14. A method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a trapping layer comprising two storage locations for storing data as non-volatile memory, the method comprising:

storing permanent data in one of said two storage locations in the trapping layer;

storing additional data to the floating body while power is applied to the memory cell;

transferring the additional data stored in the floating body to the other of said two storage locations of the trapping layer when power to the cell is interrupted; and

storing the additional data in the other of said two storage locations of the trapping layer as non-volatile memory.

15. The method of claim 14, wherein the additional data stored in the floating body is stored as volatile memory.

16. The method of claim 14, further comprising:

transferring the additional data stored in the other of said two storage locations of the trapping layer to the floating body when power is restored to the cell;

and storing the data in the floating body as volatile memory;

wherein said permanent data stored in said one of said two storage locations in the trapping layer remains unchanged when power to the cell is interrupted and when power is restored to the cell.

17. The method of claim 14, wherein the additional data transferred is stored in the other of said two storage locations of the trapping layer with a charge that is complementary to a charge of the floating body when storing the additional data.

18. The method of claim 14, wherein the transferring is a non-algorithmic process.

19. The method of claim 18 carried out on a plurality of said cells in a memory cell device, wherein the transferring is a parallel, non-algorithmic process.

20. The method of claim 16, further comprising restoring the other of said two storage locations of the trapping layer to a predetermined charge state, while leaving a state of said one of said two storage locations of the trapping layer unchanged.

21. The method of claim 16, further comprising writing a predetermined state to the floating body prior to the transferring the additional data stored in the other of said two storage locations of the trapping layer to the floating body.