PHASE TO DIGITAL CONVERTER IN ALL DIGITAL PHASE LOCKED LOOP

• US 20090256601A1
• Filed: 04/14/2008
• Published: 10/15/2009
• Est. Priority Date: 04/14/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhang, Gang, Han, Yiping, Jajoo, Abhishek
• Granted Patent: US 8,022,849 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

Claims

1. A method of phase to digital conversion, the method comprising:

initiating a first pulse based on an earlier arriving edge of one of a reference clock and an oscillator signal;

coupling the first pulse through a delay line;

determining a conversion termination signal based on a later arriving edge of one of the reference clock and the oscillator signal; and

determining a digital value of a phase difference between the reference clock and the oscillator signal based on a transition of the first pulse through the delay line.

2. The method of claim 1, wherein determining the digital value comprises determining a tapped delay line value indicative of a fractional delay through the delay line.

3. The method of claim 1, further comprising:

incrementing a counter value based on an output from the delay line; and

coupling the output from the delay line back to the input of the delay line.

4. The method of claim 3, wherein determining the digital value comprises determining the counter value.

5. The method of claim 3, wherein determining the digital value comprises:

determining the counter value as indicating a number of full transitions through the delay line; and

determining a tapped delay line value indicative of a fractional delay through the delay line.

6. The method of claim 1, wherein determining the conversion termination signal comprises initiating a second pulse based on later arriving edge of one of the reference clock and the oscillator signal.

7. The method of claim 6, wherein determining the conversion termination signal further comprises coupling the second pulse through a conversion control multiplexer, and wherein the conversion termination signal comprises an output of the conversion control multiplexer.

8. The method of claim 1, wherein initiating the first pulse based on the earlier arriving edge of one of a reference clock and an oscillator signal comprises:

determining the earlier arriving edge of one of the reference clock and the oscillator signal; and

triggering a first pulse generator based on the earlier arriving edge.

9. The method of claim 8, wherein determining the earlier arriving edge comprises:

coupling the reference clock to a non-inverting input of a D flip flop;

coupling the oscillator signal to an inverting input of the D flip flop;

clocking the D flip flop based on the logical OR of the reference clock and the oscillator signal; and

indicating the earlier arriving edge based on an output of the D flip flop.

10. A method of phase to digital conversion, the method comprising:

generating at least one phase to frequency detection signal based on transitions of an oscillator signal and transitions of a reference clock;

generating a signal pulse based on the at least one phase to frequency conversion signal; and

generating a digital value of a phase difference based on a transition of the signal pulse through a delay line.

11. The method of claim 10, wherein generating the phase difference comprises generating a fine phase difference value based in part on a partial transition of the signal pulse through the delay line.

12. The method of claim 11, wherein generating the fine phase difference comprises:

coupling the signal pulse to a tapped delay line having series connection of a plurality of delay elements; and

registering a value from each tap of the tapped delay line based on the at least one phase to frequency conversion signal.

13. The method of claim 10, wherein generating the phase difference comprises generating a coarse phase difference value based in part on a number of full transitions of the signal pulse through the delay line.

14. The method of claim 13, wherein generating the coarse phase difference comprises:

generating a read signal based on the at least one phase to frequency detection signal; and

counting a number of full transitions of the signal pulse through the delay line prior to the read signal.

15. The method of claim 10, further comprising generating a sign of the phase difference based on an order of arrival of a selected transition of the oscillator signal relative to a selected transition of the reference clock.

16. The method of claim 10, further comprising aligning a timing of rising transitions to a timing of falling transitions of the signal pulse prior to applying the signal pulse to the delay line.

17. The method of claim 10, further comprising:

incrementing a counter; and

feeding back a delayed signal pulse from an output of the delay line to generate a subsequent signal pulse based on a state of the reference clock.

18. The method of claim 10, further comprising flushing the delay line following generating the phase difference.

19. A method of phase to digital conversion, the method comprising:

receiving an oscillator signal;

receiving a reference clock;

generating at least one phase to frequency detection signal including an UP signal and a DOWN signal based on transitions of the oscillator signal and transitions of the reference clock;

generating a read signal based on the UP signal and the DOWN signal;

generating a first signal pulse based on the UP signal;

generating a second pulse signal based on the DOWN signal;

coupling the first signal pulse to a first delay line;

coupling the second pulse signal to a second delay line;

counting a number of full transitions of one of the first signal pulse or second signal pulse through its respective delay line based on transitions of the UP signal relative to the DOWN signal; and

determining a digital value of a phase difference based on at least one of the number or a partial transition of one of the first signal pulse or the second signal pulse through the respective first delay line and second delay line.

20. The method of claim 19, further comprising aligning a rising transition time and a falling transition time of the of the first signal pulse prior to coupling the first signal pulse to the first delay line.

21. The method of claim 19, further comprising:

flushing the first delay line;

flushing the second delay line;

resetting the number to a predetermined value; and

updating the digital value of the phase difference.

22. The method of claim 19, wherein coupling the first signal pulse to the first delay line comprises coupling the first signal pulse to a first tapped delay line, and wherein the digital value of the phase difference comprises a digital value based on a digital value at each tap of the first tapped delay line.

23. A phase to digital converter comprising:

a path selection multiplexer configured to receive a reference clock signal at a first input and an oscillator signal at a second input, and further configured to output one of the reference clock signal or oscillator signal based on a control input signal;

a first pulse generator having a trigger input coupled to the output of the path selection multiplexer;

a loop multiplexer configured to receive a pulse generator output at a first input and a delayed pulse signal at the second input, and configured to output one of the pulse generator output or the delayed pulse signal based on a loop control signal;

a delay line coupled to the output of the loop multiplexer and configured to output the delayed pulse signal, and further configured to indicate a fractional pulse transition upon receipt of a conversion termination signal; and

a counter configured to count a number of pulses output by the delay line and configured to output the number upon receipt of the conversion termination signal.

24. The phase to digital converter of claim 23, further comprising:

a logical OR gate configured to receive the reference clock at a first input, configured to receive the oscillator signal at a second input, and further configured to generate the logical OR of signals at the first input and second input; and

a D flip flop having a non-inverting input configured to receive the reference clock, an inverting input configured to receive the oscillator signal, and a clock input coupled to an output of the logical OR gate, and wherein the control input signal comprises an output of the D flip flop.

25. The phase to digital converter of claim 23, wherein the delay line comprises a tapped delay line.

26. The phase to digital converter of claim 23, wherein the phase to digital output comprises the number of pulses output by the delay line if the number is non-zero.

27. The phase to digital converter of claim 23, wherein the phase to digital output comprises the fractional pulse transition.

28. The phase to digital converter of claim 27, wherein the fractional pulse transition is indicated by a temperature coded digital value.

29. A phase to digital converter comprising:

a first signal processing path configured to determine a magnitude of a phase difference between an oscillator signal and a reference clock based at least one of a fractional transition of a pulse through a delay line and a number of full transitions of the pulse through the delay line; and

a sign generator configured to receive the oscillator signal and the reference clock and configured to determine a sign of the phase difference.

30. A phase to digital converter comprising:

a phase to frequency detector configured to generate an UP signal and a DOWN signal based on an oscillator signal and a reference clock;

a pulse generator coupled to the phase to frequency detector and configured to generate a pulse signal based on one of the UP signal and the DOWN signal;

a tapped delay line coupled to the pulse generator;

a counter configured to increment based on an output of the delay line;

a register coupled to the tapped delay line; and

a read control generator configured to generate a read signal based on the UP signal and the DOWN signal, and configured to latch a digital value of a phase difference in at least one of the register or the counter.

31. The phase to digital converter of claim 30, further comprising an edge aligner interposed between the pulse generator and the tapped delay line and configured to align a transition time of a rising edge of the pulse signal with a transition time of a falling edge of the pulse signal.

32. The phase to digital converter of claim 30, wherein the tapped delay line comprises a series connection of a plurality of delay elements, and wherein each tap of the tapped delay line is coupled to an output of one of the plurality of delay elements.

33. The phase to digital converter of claim 32, wherein the plurality of delay elements comprises a plurality of non-inverting buffers.

34. The phase to digital converter of claim 30, wherein the output of the delay line is fed back to the pulse generator to retrigger the pulse generator based on a state of the read signal.

35. The phase to digital converter of claim 30, wherein the digital value of the phase difference comprises the register value when the counter holds a zero value.

36. The phase to digital converter of claim 30, wherein the digital value of the phase difference comprises a counter value when the counter holds a non-zero value.

37. A phase to digital converter comprising:

means for generating a phase to frequency detection signal including an UP signal and a DOWN signal based on transitions of an oscillator signal and transitions of a reference clock;

means for generating a conversion Start signal and a conversion Stop signal based on the UP signal and the DOWN signal;

means for generating a pulse based on one of the UP signal and the DOWN signal;

means for delay coupled to the means for generating the pulse;

means for counting coupled to an output of the means for delay; and

means for converting a time to a digital value of a phase difference based on the Start signal and the Stop signal and further based on an output of the means for counting and a fractional transition of the pulse through the means for delay.

38. The phase to digital converter of claim 37, wherein the means for delay comprises:

a tapped delay line; and

a multi-bit register, wherein each bit of the multi-bit register corresponds to a tap of the tapped delay line.

39. The phase to digital converter of claim 37, further comprising

means for latching fractional transitions through the means for delay to determine the fractional transition, and

wherein the digital value of the phase difference comprises a coded output from the means for latching.

40. The phase to digital converter of claim 37, wherein the digital value of the phase difference comprises a non-zero output of the means for counting.

41. An all digital phase locked loop (ADPLL) comprising:

a digital controlled oscillator (DCO);

a digital divider having an input coupled to the DCO and an output configured to provide a digital divided output signal;

a phase to frequency detector having a first input coupled to a reference oscillator clock and a second input coupled to the output of the digital divider, the phase to frequency detector configured to generate an UP signal and a DOWN signal based on the digital divided output signal and the reference oscillator clock;

a phase to digital converter having a first input receiving the UP signal, a second input receiving the DOWN signal, and a third input receiving the reference oscillator clock, the phase to digital converter configured to generate a pulse signal based on one of the UP signal or the DOWN signal and further configured to determine a digital value of a phase difference between the digital divided output signal and the reference oscillator clock based on at least one of full transitions of the pulse signal through a delay line and partial transitions of the pulse through the delay line; and

a digital loop filter having an input coupled to an output of the phase to digital converter and an output coupled to a control input of the DCO.

42. The ADPLL of claim 41, further comprising:

a modulator; and

a combiner with a first input coupled to the output of the digital loop filter, a second input coupled to an output of the modulator, and an output coupled to the control input of the DCO.

43. The ADPLL of claim 41, wherein the digital divider comprises a fractional divider.

44. The ADPLL of claim 41, wherein the phase to digital converter comprises:

a pulse generator coupled to the phase to frequency detector and configured to generate the pulse signal based on one of the UP signal and the DOWN signal;

a counter configured to increment based on an output of the delay line;

a register coupled to the delay line and configured to determine a digital value representative of the partial transitions of the pulse signal through the delay line; and

a read control generator configured to generate a read signal based on the UP signal and the DOWN signal, and configured to latch a digital value of the phase difference in at least one of the register or the counter.