RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES

• US 20090256752A1
• Filed: 04/14/2008
• Published: 10/15/2009
• Est. Priority Date: 04/14/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Floyd, Brian A., Liu, Duixian, Akkermans, Johannes A.G.
• Granted Patent: US 7,696,930 B2
• Time in Patent Office: Days
• US Class Current: 343/700.MS
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07786 the antenna being of the HF type, such as a dipole
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15323 being a land array, e.g. LGA
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H01Q 21/065 Patch antenna array
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/0457 electromagnetically coupled to the feed line
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making

Abstract

A radio-frequency integrated circuit chip package has N integrated aperture-coupled patch antennas, N being at least two, and includes N generally planar patches, and at least one generally planar ground plane spaced inwardly from the N generally planar patches and substantially parallel thereto. The ground plane is formed with at least N coupling aperture slots therein, and the slots are substantially opposed to the patches. N feed lines are spaced inwardly from the ground plane and substantially parallel thereto, and at least one radio frequency chip is spaced inwardly from the feed lines and coupled to the feed lines and the ground plane. A first substrate layer is spaced inwardly from the feed lines, and is formed with a chip-receiving cavity, with the chip located in the chip-receiving cavity. A second substrate layer is interposed in a region between the ground plane and a plane defined by the patch, the patch is formed in a first metal layer, the ground plane is formed in a second metal layer, and the second substrate layer defines an antenna cavity in which the N generally planar patches are located. “Island” and “offset” configurations, as well as fabrication methods, are also disclosed.

Claims

1. A radio-frequency integrated circuit chip package with N integrated aperture-coupled patch antennas, N being at least two, said package comprising:

N generally planar patches;

at least one generally planar ground plane spaced inwardly from said N generally planar patches and substantially parallel thereto, said ground plane being formed with at least N coupling aperture slots therein, said slots being substantially opposed to said patches;

N feed lines spaced inwardly from said ground plane and substantially parallel thereto;

at least one radio frequency chip spaced inwardly from said feed lines and coupled to said feed lines and said ground plane;

a first substrate layer spaced inwardly from said feed lines, said first substrate layer being formed with a chip-receiving cavity, said chip being located in said chip-receiving cavity; and

a second substrate layer interposed in a region between said ground plane and a plane defined by said patch, wherein;

said patch is formed in a first metal layer;

said ground plane is formed in a second metal layer; and

said second substrate layer defines an antenna cavity, said N generally planar patches being located in said antenna cavity.

2. The package of claim 1, further comprising an island formed in said second substrate layer, within said antenna cavity, thus defining a ring shape of said cavity, said island being substantially opposed to said chip-receiving cavity.

3. The package of claim 2, wherein said island and said antenna cavity are substantially rectangular when viewed in plan.

4. The package of claim 2, wherein said island and said antenna cavity are substantially circular when viewed in plan.

5. The package of claim 2, further comprising a third substrate layer interposed in a region between said ground plane and said feed lines, wherein said feed lines are formed in a third metal layer.

6. The package of claim 5, further comprising N reflectors spaced inwardly from said third substrate layer and generally opposed to said coupling aperture slots.

7. The package of claim 6, wherein said reflectors are located on an inner surface of said first substrate layer.

8. The package of claim 7, further comprising a fourth substrate layer spaced inwardly from said reflectors, said reflectors being embedded between said first and fourth substrate layers.

9. The package of claim 2, further comprising a cover, wherein said island is configured to support said cover.

10. The package of claim 1, wherein said N patches are arranged to form a planar phased array.

11. The package of claim 1, wherein said antenna cavity is spaced away from said chip-receiving cavity when viewed in plan, such that loads incurred during insertion of said chip into said chip-receiving cavity are substantially supported away from said antenna cavity.

12. The package of claim 1, wherein said ground plane is formed with at least 2N of said coupling aperture slots therein, two of said coupling aperture slots for each of said patches.

13. A method of fabricating a radio-frequency integrated circuit chip package with N integrated aperture-coupled patch antennas, N being at least two, said method comprising the steps of:

providing a package comprising;

N generally planar patches;

at least one generally planar ground plane spaced inwardly from said N generally planar patches and substantially parallel thereto, said ground plane being formed with at least N coupling aperture slots therein, said slots being substantially opposed to said patches;

N feed lines spaced inwardly from said ground plane and substantially parallel thereto;

a first substrate layer spaced inwardly from said feed lines, said first substrate layer being formed with a chip-receiving cavity;

a second substrate layer interposed in a region between said ground plane and a plane defined by said patch, wherein;

said patch is formed in a first metal layer;

said ground plane is formed in a second metal layer; and

said second substrate layer defines an antenna cavity, said N generally planar patches being located in said antenna cavity; and

an island formed in said second substrate layer, within said antenna cavity, thus defining a ring shape of said cavity, said island being substantially opposed to said chip-receiving cavity; and

inserting at least one radio frequency chip into said chip-receiving cavity, with said island supporting loads induced by said insertion of said chip into said chip-receiving cavity.

14. The method of claim 13, further comprising the additional step of securing a cover over said antenna cavity, with said cover being supported, at least in part by said island.

15. A method of fabricating a radio-frequency integrated circuit chip package with N integrated aperture-coupled patch antennas, N being at least two, said method comprising the steps of:

providing a package comprising;

N generally planar patches;

at least one generally planar ground plane spaced inwardly from said N generally planar patches and substantially parallel thereto, said ground plane being formed with at least N coupling aperture slots therein, said slots being substantially opposed to said patches;

N feed lines spaced inwardly from said ground plane and substantially parallel thereto;

a first substrate layer spaced inwardly from said feed lines, said first substrate layer being formed with a chip-receiving cavity;

a second substrate layer interposed in a region between said ground plane and a plane defined by said patch, wherein;

said patch is formed in a first metal layer;

said ground plane is formed in a second metal layer;

said second substrate layer defines an antenna cavity, said N generally planar patches being located in said antenna cavity; and

said antenna cavity is spaced away from said chip-receiving cavity when viewed in plan; and

inserting at least one radio frequency chip into said chip-receiving cavity, such that loads incurred during insertion of said chip into said chip-receiving cavity are substantially supported away from said antenna cavity.