METHODS OF FABRICATING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS ON SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES FABRICATED THEREBY

• US 20090258463A1
• Filed: 04/07/2009
• Published: 10/15/2009
• Est. Priority Date: 04/10/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Myung-Sun, Rhee, Hwa-Sung, Lee, Ho, Yi, Ji-Hye
• Granted Patent: US 8,207,033 B2
• Time in Patent Office: Days
• US Class Current: 438/142
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

Claims

1. A method of fabricating a semiconductor integrated circuit device, comprising:

providing a substrate with gate patterns formed on first and second regions, wherein spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region;

forming source/drain trenches in the substrate on opposite sides of the gate patterns on the first and second regions;

forming a first silicon-germanium (SiGe) epitaxial layer that partially fills the source/drain trenches using a first silicon source gas; and

forming a second SiGe epitaxial layer directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

2. The method of claim 1, wherein:

the first silicon source gas comprises a dichlorosilane gas; and

the second silicon source gas comprises a silane gas.

3. The method of claim 1, wherein:

the first silicon source gas comprises a silane gas; and

the second silicon source gas comprises a dichlorosilane gas.

4. The method of claim 1, wherein forming the first SiGe epitaxial layer comprises growing the first SiGe epitaxial layer on exposed portions of the substrate on the first region at a greater rate than the first SiGe epitaxial layer is grown on exposed portions of the substrate on the second region so that the first SiGe epitaxial layer in the source/drain trenches on the first region is thicker than the first SiGe epitaxial layer in the source/drain trenches on the second region.

5. The method of claim 4, wherein forming the second SiGe epitaxial layer comprises growing the second SiGe epitaxial layer on the first SiGe epitaxial layer on the second region at a greater rate than the second SiGe epitaxial layer is grown on the first SiGe epitaxial layer on the first region, so that the second SiGe epitaxial layer on the second region is thicker than the second SiGe epitaxial layer on the first region, and so that a sum of the thicknesses of the first and second SiGe epitaxial layers is substantially the same in the first and second regions.

6. The method of claim 1, wherein forming the first SiGe epitaxial layer comprises forming the first SiGe epitaxial layer in the second region with a thickness that is greater than a thickness of the first SiGe epitaxial layer in the first region.

7. The method of claim 1, wherein the first region comprises device structures that define a cell region, the second region comprises device structures that define a peripheral circuit region, and the device structures in the cell region have a higher density than the device structures in the peripheral circuit region.

8. The method of claim 1, wherein the first and second source gases comprise first and second germanium source gases having different germanium content from each other.

9. The method of claim 1, wherein the first and second silicon source gases have different growth profiles.

10. The method of claim 1, further comprising forming a silicide layer on the second SiGe epitaxial layer after the second SiGe epitaxial layer has been formed.

11. The method of claim 1, wherein forming the first and second SiGe epitaxial layers comprises forming the first and second SiGe epitaxial layers with different thicknesses.

12. A method of fabricating a semiconductor integrated circuit device, comprising:

forming a plurality of gate patterns on a wafer within a center region and within an edge region of the wafer;

forming source/drain trenches in the wafer on opposite sides of the gate patterns on the center and edge regions;

forming a first silicon-germanium (SiGe) epitaxial layer that partially fills the source/drain trenches using a first silicon source gas; and

forming a second SiGe epitaxial layer directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

13. The method of claim 12, wherein the forming the first SiGe epitaxial layer comprises forming the first SiGe epitaxial layer in the source/drain trenches on the center region to have a greater thickness than the first SiGe epitaxial layer in the source/drain trenches on the edge region.

14. The method of claim 12, wherein:

the first silicon source gas comprises a dichlorosilane gas; and

the second silicon source gas comprises a silane gas.

15. The method of claim 12, wherein the first and second source gases comprise first and second germanium source gases having different germanium content from each other.

16. A semiconductor integrated circuit device comprising:

a substrate include gate patterns on a first region and on a second region, wherein spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region;

source/drain trenches in the substrate on opposite sides of the gate patterns;

a first silicon-germanium (SiGe) epitaxial layer that partially fills the source/drain trenches, wherein thicknesses of the first SiGe epitaxial layer on the first and second regions are different from each other; and

a second SiGe epitaxial layer that is on the first SiGe epitaxial layer.

17. The semiconductor integrated circuit device of claim 16, wherein a thickness of the first SiGe epitaxial layer in the source/drain trenches on the first region is larger than a thickness of the first SiGe epitaxial layer in the source/drain trenches on the second region.

18. The semiconductor integrated circuit device of claim 17, wherein the second SiGe epitaxial layer is formed on the first SiGe epitaxial layer on the second region with a greater thickness than the second SiGe epitaxial layer that is formed on the first SiGe epitaxial layer on the first region, and so that a sum of the thicknesses of the first and second SiGe epitaxial layers on the first and second regions is substantially the same.

19. The semiconductor integrated circuit device of claim 16, wherein the first and second SiGe epitaxial layers have different germanium densities.

20. The semiconductor integrated circuit device of claim 16, wherein the first and second SiGe epitaxial layers are formed with different thicknesses on the first and second regions.

21. The semiconductor integrated circuit of claim 16, further comprising a silicide layer on the second SiGe epitaxial layer opposite to the first SiGe epitaxial layer.