LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS

• US 20090259783A1
• Filed: 06/23/2009
• Published: 10/15/2009
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Doron Solomon, Gilad Garon
• Original Assignee: Doron Solomon, Gilad Garon
• Inventors: Garon, Gilad, Solomon, Doron
• Granted Patent: US 9,448,963 B2
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

Claims

1. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:

a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and

a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;

wherein at least some of the same megafunctions are used with algorithms of two or more protocols.

2. The chip architecture according to claim 1, wherein at least some of the megafunctions are parameterized, the parameters of at least some of the megafunctions are adapted to be dynamically changed depending on the communication protocol.

3. The chip architecture according to claim 2, further including buses interconnecting the megafunctions, and wherein the size of at least some of the buses are adapted to be dynamically changed depending on the communication protocol.

4. The chip architecture according to claim 2, wherein the control signals for changing parameters of the parameterized megafunctions are stored in memory.

5. The chip architecture according to claim 2, wherein the control signals for changing the parameters of the parameterized megafunctions are inserted on-line from outside the chip architecture.

6. The chip architecture according to claim 1, wherein the control signals are stored in memory.

7. The chip architecture according to claim 1, wherein the control signals are inserted on-line from outside the chip architecture.

8. The chip architecture according to claim 1, further including an interconnect network among the megafunctions, and memory for storing a set of signals for reconfiguring the megafunctions and interconnect network between the megafunctions so as to set the parameters and algorithms associated with the protocol of the signals being processed.

9. The chip architecture according to claim 1, further including an analyzer configured so as to determine the protocol of the signal processed by the chip architecture, and apply the necessary control signals so as to configure the switches and interconnect the necessary megafunctions for processing the signals according to the determined protocols.

10. The chip architecture according to claim 9, wherein the analyzer is an algorithm performed by the system architecture.

11. The chip architecture according to claim 10, wherein the analyzer is an algorithm for checking the strength of the signals processed by the chip architecture.

12. The chip architecture according to claim 9, wherein the analyzer is responsive to the user input to the system architecture.

13. The chip architecture according to claim 1, further including a control for sensing the protocol of the signal, and operating the switches and configuring the megafunctions accordingly.

14. The chip architecture according to claim 1, wherein the protocol for processing of the signal is determined by a hand-off protocol between communication standards.

15. The chip architecture according to claim 1, wherein at least one protocol implements the same algorithm at different stages of the protocol, as a function of a change in the receipt/transmission conditions.

16. The chip architecture according to claim 1, wherein at least one protocol implements the same algorithm at different megafunctions of the same stage of the protocol as a function of a change in the receipt/transmission conditions.

17. The chip architecture for use in processing signals encoded in accordance with any one of a plurality of protocols each defined by a series of algorithms, comprising:

a plurality of megafunctions;

a plurality of switches configured to selectively interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; and

memory for storing control signals applied to the switches as a function of the protocol of the signals to be processed.

18. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving orthogonal transforms of said signals.

19. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving cosine and sine transforms.

20. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving Hilbert transforms.

21. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving Walsh functions.

22. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving Fourier transforms.

23. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement algorithms involving Walsh-Hadamard transforms.

24. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to perform processing of trellises defining the signals.

25. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a search of the minimum/maximum weight path, the BCJR algorithm for calculation of a MAP, and a belief propagation algorithm.

26. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement matrix-vector operations.

27. The chip architecture according to claim 26, wherein one or more of the megafunctions is configured to implement matrix-vector operations in finite and/or infinite fields.

28. The chip architecture according to claim 26, wherein one or more of the megafunctions is configured to implement additional operations supported by the matrix-vector operations including polynomial convolutions and vector coordinate permutations.

29. The chip architecture according to claim 17, wherein at least one or more of the megafunctions is configured to implement a process including multiplication of matrices by vectors, scalar product of vectors, and interleaving.

30. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of decoding convolution codes.

31. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of decoding turbo codes.

32. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of decoding low density parity check (LDPC) codes.

33. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of decoding algebraic codes.

34. The chip architecture according to claim 17, wherein the algebraic codes include Reed-Solomon codes.

35. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of equalization of the processed signals.

36. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of synchronizing the processed signals.

37. The chip architecture according to claim 17, wherein at least one protocol implements a space-time coding/decoding function.

38. The chip architecture according to claim 17, wherein one or more of the megafunctions is configured to implement a process of MIMO processing of the processed signals.

39. A chip architecture comprising:

a controller for operating the plurality of switches so that different megafunctions can be interconnected to implement the same algorithm at the different stages in order provide efficient allocation of resources for implementing the protocol.

40. The chip architecture according to claim 39, wherein at least one of the megafunctions is parameterized, and at least one parameter of the least one megafunction is set by an on-line condition, wherein the same algorithm is implemented by the same megafunction with the parameter set by the on-line condition.

41. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:

an input/output for receiving input data and providing output processed data;

memory for storing instructions relating to the configuration of the chip for each of the protocols;

a plurality of megafunctions configured to be interconnected in each of plurality of configurations, at least one configuration corresponding to each of the communication protocols;

a plurality of switches configured and responsive to control signals so as to interconnect the megafunctions in each of the plurality of configurations as determined by the communication protocol of the encoded signals;

a reconfigurable net bus for interconnecting the switches, megafunctions and input/output; and

a CPU configured to control the configuration of the megafunctions, switches and buses as a function of the communication protocol of the encoded signals.

42. The chip architecture according to claim 41, wherein at least some of the megafunctions include reconfigurable parameters, and the CPU is configured to control the configuration of the megafunctions, switches and net bus including dynamic control of the reconfigurable parameters.

43. The chip architecture according to claim 42, wherein the memory includes RAM configured to store compiled software instructions.

44. The chip architecture according to claim 42, further including a variable clock applied to different megafunctions and configured to allow parallel processing of data at different clocking rates.

45. The chip architecture according to claim 41, wherein the CPU includes a processor configured to implement higher layer protocols.

46. The chip architecture according to claim 41, further including an enabler for applying a periodic enabling signal to different ones of the megafunctions.

47. A wireless communication device for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:

an antenna for receiving and transmitting a signal encoded in accordance with anyone of a plurality of communication protocols;

a baseband processor for processing the signals received and transmitted by the antenna;

configware comprising;

a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and

a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;

wherein at least some of the same megafunctions are used with algorithms of two or more protocols.

48. The wireless communication device according to claim 47, wherein the wireless device includes a transmitter, and the baseband processor encodes the processed signal in accordance with any one of said protocols prior to transmitting the signal.

49. The wireless communication device according to claim 47, wherein the wireless device includes a receiver, and the baseband processor decodes the processed signal in accordance with any one of said protocols after receiving the processed signal.

50. The wireless communication device according to claim 47, wherein the wireless device is adapted to transmit and receive, and the baseband processor is configured to encode the processed signal in accordance with any one of the protocols prior to transmitting an encoded signal, and decode the processed signal in accordance with any one of said protocols after receiving the processed signal.

51. A method of manufacturing a chip with an architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising creating configware so as to include:

a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and

a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;

wherein at least some of the same megafunctions are used with algorithms of two or more protocols.