TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT

• US 20090259900A1
• Filed: 03/17/2009
• Published: 10/15/2009
• Est. Priority Date: 11/23/1999
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Granted Patent: US 7,900,104 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318371 Methodologies therefor, e.g. algorithms, procedures
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

Claims

1-30. -30. (canceled)

31. A computer-readable medium storing computer-executable instructions for causing a computer to perform a method for computing a compressed test pattern for testing an integrated circuit, the method comprising:

generating symbolic expressions that are associated with scan cells, the symbolic expressions being a function of input variables to be applied concurrently while the scan cells are being loaded;

generating a test cube having the scan cells assigned predetermined values; and

formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions.

32. The computer-readable medium of claim 31, wherein the values assigned to the scan cells are chosen to test potential faults in the integrated circuit.

33. The computer-readable medium of claim 31, wherein the method further includes solving the equations to obtain the compressed test pattern and, after solving the equations, incrementally appending the set of equations with one or more equations.

34. The computer-readable medium of claim 33, wherein the method further includes:

(a) attempting to solve the appended set of equations;

(b) if the attempt to solve the equations fails, deleting the most recently appended equations and appending one or more different equations onto the set of equations; and

(c) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations; and

(d) repeating (a)-(c) until a predetermined limiting criteria is reached.

35. The computer-readable medium of claim 31, wherein generating symbolic expressions includes:

assigning the input variables to bits on input channels to the integrated circuit, wherein the number of input variables is larger than the number of channels;

simulating the application of the input variables to a decompressor in the integrated circuit and simulating that the decompressor is continually clocked to decompress the input variables, wherein one or more additional input variables are injected into the decompressor during one or more clock cycles; and

generating a set of output expressions from the decompressor that results from the simulation, wherein the output expressions are based on the input variables that are injected as the decompressor is continually clocked.

36. The computer-readable medium of claim 35, wherein the method further includes assigning each of the output expressions to each scan cell within a scan chain in the integrated circuit.

37. The computer-readable medium of claim 31, wherein the method further includes solving the equations and wherein solving the equations includes performing a Gauss-Jordon elimination method for solving equations.

38. The computer-readable medium of claim 31, wherein the method further includes generating a test cube includes assigning values of a predetermined logic 1 or a predetermined logic 0 to the scan cells for testing a fault in the integrated circuit.

39. The computer-readable medium of claim 31, wherein formulating the set of equations includes:

associating each symbolic expression in a one-to-one relationship with a scan cell; and

for each scan cell having a predetermined assigned value, equating the symbolic expression associated with that scan cell to the predetermined assigned value.

40. The computer-readable medium of claim 31, wherein generating symbolic expressions includes using simulation of a decompressor or a mathematical representation of a decompressor.

41. A system for computing a compressed test pattern for testing an integrated circuit design, the system comprising:

means for generating symbolic expressions that are associated with scan cells, the symbolic expressions being a function of input variables to be applied concurrently while the scan cells are being loaded;

means for generating a test cube having the scan cells assigned predetermined values; and

means for formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions.

42. A computer-readable medium storing computer-executable instructions for causing a computer to perform a method, the method comprising:

(a) generating a preliminary set of equations associated with the compressed test pattern;

(b) attempting to solve the set of equations;

(c) if the attempt to solve the equations fails, deleting a most recently appended equation;

(d) if the attempt to solve the equations is successful, incrementally appending additional equations onto the set of equations;

(e) repeating (b), (c) and (d) to generate a final set of equations; and

(f) solving the final set of equations to obtain the compressed test pattern.

43. The computer-readable medium of claim 42, wherein the repeating occurs until a predetermined limiting criteria is reached.

44. The computer-readable medium of claim 42, wherein the method further includes generating symbolic expressions associated with scan cells within the integrated circuit, the symbolic expressions being associated with input variables to be applied concurrently while the scan cells are being loaded.

45. The computer-readable medium of claim 44, wherein the method further includes generating symbolic expressions including:

assigning input variables to bits on input channels to the integrated circuit, wherein the number of input variables is larger than the number of channels;

simulating the application of the input variables to a decompressor in the integrated circuit and simulating that the decompressor is continually clocked to decompress the input variables, wherein one or more additional input variables are injected into the decompressor during one or more clock cycles; and

generating a set of output expressions from the decompressor that results from the simulation, wherein the output expressions are based on the input variables that are injected as the decompressor is continually clocked.

46. The computer-readable medium of claim 45, wherein the method further includes assigning each of the output expressions to each scan cell within a scan chain in the integrated circuit.

47. The computer-readable medium of claim 42, wherein solving the equations includes performing a Gauss-Jordon elimination method for solving equations.

48. The computer-readable medium of claim 42, wherein the method further includes generating a test cube including assigning values of a predetermined logic 1 or a predetermined logic 0 to scan cells for testing a fault in the integrated circuit.

49. The computer-readable medium of claim 42, wherein the method further includes:

(a) applying the compressed test pattern to the integrated circuit;

(b) decompressing the test pattern; and

(c) loading scan cells within the integrated circuit with the decompressed test pattern, wherein (a), (b) and (c) occur substantially concurrently.

50. The computer-readable medium of claim 42, wherein generating the final set of equations includes:

associating symbolic expressions in a one-to-one relationship with a scan cell; and

for each scan cell having a predetermined assigned value, equating the symbolic expression associated with that scan cell to the predetermined assigned value.

51. The computer-readable medium of claim 42, wherein the method further includes generating symbolic expressions that are associated with scan cells in the integrated circuit, wherein generating symbolic expressions includes using a mathematical representation of a decompressor.