METHOD, DEVICE, AND SYSTEM FOR PRE-MEMORY SYMMETRIC MULTIPROCESSING FLOW

• US 20090271601A1
• Filed: 04/25/2008
• Published: 10/29/2009
• Est. Priority Date: 04/25/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sakthikumar, Palsamy, ZIMMER, Vincent J.
• Granted Patent: US 8,078,862 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A cache-as-RAM (CAR) system of a multi-processor system that includes a plurality of processors may be initialized. The CAR system may assign a physical data address range for each of the plurality of processors such that the physical data address ranges allocated to all of the plurality of processors overlap with each other. A boot code stream may be executed with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream. Other embodiments are described and claimed.

Claims

1. A method comprising:

initializing a cache-as-RAM (CAR) system in a multi-processor system, the multi-processor system including at least a plurality of processors, each processor associated with a memory;

the CAR system assigning a physical data address range for each of the plurality of processors, such that the physical data address ranges allocated to all of the plurality of processors overlap with each other; and

executing a boot code stream with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream.

2. The method of claim 1, wherein changes to a cache state while executing the boot code stream are made without a writeback to a main memory.

3. The method of claim 1, wherein changes to a cache state while executing the boot code stream are executed using a Modified/Exclusive/Shared/Invalid/Forward protocol.

4. The method of claim 1, wherein the physical address ranges allocated to all of the plurality of processors overlap completely with each other.

5. The method of claim 1, wherein a plurality of first parts of the physical address ranges allocated to all of the plurality of processors overlap completely with each other and a plurality of second parts of the physical address ranges are assigned uniquely to each of the plurality of processors.

6. The method of claim 1, wherein one or more interconnects of the multi-processor system comprise point to point interconnects.

7. A device comprising:

a plurality of processors each associated with a portion of memory, one or more of the plurality of processors to initialize a cache-as-RAM (CAR) system, to assign by the CAR system a tile for each of a plurality of processors such that the tiles allocated to all of the plurality of processors overlap with each other, and to execute a boot code stream with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream.

8. The device of claim 7, wherein changes to a cache state while executing the boot code stream are made without a writeback to a main memory.

9. The device of claim 7, wherein changes to a cache state while executing the boot code stream are executed using a Modified/Exclusive/Shared/Invalid/Forward protocol.

10. The device of claim 7, wherein the tiles allocated to all of the plurality of processors overlap completely with each other.

11. The device of claim 7, wherein a plurality of first parts of the tiles allocated to all of the plurality of processors overlap completely with each other and a plurality of second parts of the tiles are assigned uniquely to each of the plurality of processors.

12. The device of claim 7, wherein one or more interconnects of the multi-processor system comprise point to point interconnects.

13. A system comprising:

a plurality of processors each associated with a memory, one or more of the plurality of processors to initialize a cache-as-RAM (CAR) system, to assign by the CAR system a physical data address range for each of the plurality of processors such that the physical data address ranges allocated to all of the plurality of processors overlap with each other, and to execute a boot code stream with the CAR accessed by the executing boot stream as a memory store for executing the boot code stream; and

an interconnect network to connect the plurality of processors.

14. The system of claim 13, wherein changes to a cache state while executing the boot code stream are made without a writeback to a main memory.

15. The system of claim 13, wherein changes to a cache state while executing the boot code stream are executed using a Modified/Exclusive/Shared/Invalid/Forward protocol.

16. The system of claim 13, wherein the physical address ranges allocated to all of the plurality of processors overlap completely with each other.

17. The system of claim 13, wherein a first part of the physical address ranges allocated to all of the plurality of processors overlap completely with each other and a plurality of second parts of the physical address ranges are assigned uniquely to each of the plurality of processors.

18. The system of claim 13, wherein the interconnect network comprises a point to point interconnect network.

19. A processor-readable storage medium having stored thereon instructions that, if executed by a processor, cause the processor to perform a method comprising:

initializing a cache-as-RAM (CAR) system in a multi-processor system, the multi-processor system including at least a plurality of processors, each processor associated with a memory;

the CAR system assigning a tile for each of the plurality of processors, such that the tiles allocated to all of the plurality of processors overlap with each other; and

a boot code stream accessing the CAR as a memory store for execution.

20. The processor-readable storage medium of claim 19, further comprising instructions that if executed by a processor, cause the processor to perform the method wherein changes to a cache state during execution of the boot code stream are made without a writeback to a main memory.

21. The processor-readable storage medium of claim 19, further comprising instructions that if executed by a processor, cause the processor to perform the method wherein the tiles allocated to all of the plurality of processors overlap completely with each other.

22. The processor-readable storage medium of claim 19, further comprising instructions that if executed by a processor, cause the processor to perform the method wherein a plurality of first parts of the tiles allocated to all of the plurality of processors overlap completely with each other and a plurality of second parts of the tiles are assigned uniquely to each processor of the plurality of processors.