Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit

• US 20090273966A1
• Filed: 05/02/2008
• Published: 11/05/2009
• Est. Priority Date: 05/02/2008
• Status: Active Grant

• Current Assignee: Altis Semiconductor (Altis International), Infineon Technologies AG
• Original Assignee: Altis Semiconductor (Altis International), Qimonda AG (Infineon Technologies AG)
• Inventors: Leuschner, Rainer, Klostermann, Ulrich, Gogl, Dietmar
• Granted Patent: US 7,903,454 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

Claims

1. An integrated circuit comprising a plurality of thermal selectable memory cells,

each memory cell being coupled to a conductive line, the conductive line comprising a first portion for applying a heating current, and a second portion for applying a programming current,

the integrated circuit being configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

2. The integrated circuit according to claim 1, wherein a first end of the conductive line is coupled to a first area set to a first potential, and wherein a second end of the conductive line is coupled via a switch to a second area set to a second potential.

3. The integrated circuit according to claim 2, wherein the first potential and the second potential are fixed potentials.

4. The integrated circuit according to claim 3, further comprising a potential controlling unit is coupled between the second area and the switch, wherein the potential controlling unit controls a potential drop between the second area and the second end of the conductive line such that the potential of the second end of the conductive line is controlled to a third potential.

5. The integrated circuit according to claim 4, wherein the third potential is a fixed potential.

6. The integrated circuit according to claim 4, wherein the potential controlling unit comprises a tunable resistor.

7. The integrated circuit according to claim 4, wherein the potential controlling unit comprises a transistor current source.

8. The integrated circuit according to claim 3, wherein the second potential is a ground potential.

9. The integrated circuit according to claim 1, wherein the conductive line is a bit line or a part of a bit line.

10. The integrated circuit according to claim 9, wherein a first end of the conductive line is coupled to a first area set to a first potential, and wherein a second end of the conductive line is coupled via a switch to a second area set to a second potential and wherein the first area is located within a bit line multiplexer.

11. The integrated circuit according to claim 10, wherein a potential controlling unit is coupled between the second area and the switch, wherein the bit line multiplexer, the switch and the potential controlling unit are coupled to a programming current controlling unit which controls the bit line multiplexer, the switch and the potential controlling unit such that the programming current routed through the bit line is controlled to a constant value.

12. A memory cell array comprising a plurality of thermal selectable memory cells,

each memory cell being coupled to a bit line comprising a first portion for applying a heating current, and a second portion for applying a programming current,

the memory cell array being configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the bit line independently from each other.

13. A memory module, the memory module comprising at least one memory cell array according to claim 12.

14. A method of operating an integrated circuit comprising an arrangement of thermal selectable memory cells, each memory cell being coupled to a conductive line,

the method comprising:

routing a heating current through the memory cell in order to heat the memory cell, wherein the heating current is routed through a first portion of the conductive line assigned to the memory cell, and

routing a programming current through a second portion of the conductive line in order to program the memory cell,

wherein the routing of the programming current is carried out independently from the routing of the heating current.

15. The method according to claim 14, wherein the programming current and the heating current are routed through the conductive line simultaneously.

16. The method according to claim 14, wherein the routing of the programming current through the conductive line is started immediately after having terminated the routing of the heating current through the conductive line.

17. The method according to claim 14, wherein the routing of the programming current through the conductive line is started within 1 ns to 5 ns after having terminated the routing of the heating current through the conductive line.

18. The method according to claim 14, wherein the routing direction of the heating current is chosen in dependence on a memory value to be written into the memory cell.

19. The method according to claim 14, wherein a first end of the conductive line is coupled to a first area set to a first potential, and wherein a second end of the conductive line is connected via a switch to a second area set to a second potential.

20. The method according to claim 19, wherein the first and second potentials are fixed potentials.

21. The method according to claim 19, wherein, in order to route the programming current through the conductive line, the switch is closed.

22. The method according to claim 21, wherein the switch is closed during the routing of the heating current through the conductive line.

23. The method according to claim 21, wherein the switch is closed immediately after having terminated the routing of the heating current.

24. The method according to claim 21, wherein the switch is closed within 1 ns to 5 ns after having terminated the routing of the heating current.

25. The method according to claim 19, wherein the potential of the second end of the conductive line is controlled to a third potential by controlling a potential drop between the second area and the second end of the conductive line.