PIPELINE METHOD AND SYSTEM FOR SWITCHING PACKETS

• US 20090279548A1
• Filed: 01/08/2007
• Published: 11/12/2009
• Est. Priority Date: 05/06/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Aris, Davis, Ian Edward
• Granted Patent: US 7,813,367 B2
• Time in Patent Office: Days
• US Class Current: 370/394
• CPC Class Codes: H04L 49/1546 using pipelined operation

Abstract

A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Claims

1. In a switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure, a method for switching packets rapidly between one or more source devices and one or more destination devices, the method comprising:

pipelining packets through a series of first processing segments to perform a plurality of first sub-operations involved in initial processing of packets received from source devices to be buffered in the memory structure;

pipelining packets through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission; and

pipelining packets through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

2. The method of claim 1, wherein pipelining packets through first, second or third processing segments comprises storing packets in process in a plurality of FIFOs situated between first, second, or thirds processing segments, respectively.

3. The method of claim 1, wherein pipelining packets through first, second or third processing segments comprises pipelining a packet through the respective processing segments in four processor clocks.

4. The method of claim 1, wherein pipelining packets through first processing segments comprises pipelining packets through two or more first sub-operations selected from the group consisting of:

packet classification, CAM lookup, PRAM lookup, packet header generation for forwarding packets through a chassis, and preparation of packet modifications.

5. The method of claim 1, wherein pipelining packets through second processing segments comprises pipelining packets through two or more second processing segments to dispatch packets to a backplane interface.

6. The method of claim 5, wherein pipelining packets through second processing segments comprises pipelining packets through two or more second sub-operations selected from the group consisting of:

retrieval of data from the memory structure, receipt of packet length and priority data, forwarding identifier lookup, port mask merging, and backplane dispatch.

7. The method of claim 1, wherein pipelining packets through second processing segments comprises pipelining packets through two or more second sub-operations selected from the group consisting of:

backplane packet collection, organization of packets according to source or priority, and end-of-packet detection.

8. The method of claim 1, wherein pipelining packets through third processing segments comprises pipelining packets through two or more third sub-operations selected from the group consisting of:

packet availability detection, ordered packet retrieval, forwarding identifier lookup, VLAN tag replacement, packet header processing for replacing MAC addresses, and VLAN tag insertion.

9. A system for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:

a first data pipeline, the first data pipeline used to couple a media access control (MAC) interface to facilitate receipt and transmission packets over a physical interface, a receive packet processor configured to perform initial processing of received packets that are buffered in a first memory, and a backplane manager configured to compute an appropriate destination and dispatch packets on the backplane; and

a second data pipeline, the second data pipeline used to couple a transmission accumulator configured to receive packets from the backplane and organize the packets for transmission that are buffered in a second memory, a transmit packet processor configured to schedule the transmission of packets, and the MAC interface.

10. The system of claim 9 wherein the first and second data pipelines comprise a plurality of FIFO structures within each of the processors to provide for pipelined processing of data.

11. The system of claim 10 wherein the receive packet processor, the backplane manager, the transmission accumulator and the transmit packet processor are field programmable gate arrays.

12. The system of claim 10 wherein the receive packet processor, the backplane manager, the transmission accumulator and the transmit packet processor are application specific integrated circuits.

14. A method for switching data between one or more source devices and one or more destination devices, the method comprising:

pipelining data between a media access control (MAC) interface, a receive packet processor coupled to the MAC interface and a first memory, the receive packet processor configured to perform initial processing of received packets to be buffered in the first memory, and a backplane manager coupled to the first memory and a backplane, the backplane manager configured compute an appropriate destination and dispatch packets to the backplane; and

pipelining data between a transmission accumulator coupled to the backplane and a second memory, the transmission accumulator configured to organize packets received from the backplane for transmission to the second memory, and a transmit packet processor coupled to the second memory and the MAC interface, the transmit packet processor configured to schedule the transmission of packets to the MAC interface.

15. A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure, the processors being programmed or wired to pipeline packets for switching packets rapidly between one or more source devices and one or more destination devices, the device comprising:

a first series of processing segments for pipelining packets through a plurality of first sub-operations involved in initial processing of packets received from source devices to be buffered in the memory structure;

a second series of processing segments for pipelining packets through a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission; and

a third series of processing segments for pipelining packets through a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

13. The system of claim 20 wherein the first and second memories are dualport memories.

16. The device of claim 15, comprising a plurality of FIFOs situated between first, second, or third processing segments for storing packets in process through first, second or third processing segments, respectively.

17. The device of claim 15, wherein the first sub-operations performed by first processing segments are selected from the group consisting of:

packet classification, CAM lookup, PRAM lookup, packet header generation for forwarding packets through a chassis, and preparation of packet modifications.

18. The device of claim 15, wherein the second series of processing segments for pipelining packets dispatch packets to a backplane interface.

19. The device of claim 18, wherein the second sub-operations performed by second processing segments are selected from the group consisting of:

retrieval of data from the memory structure, receipt of packet length and priority data, forwarding identifier lookup, port mask merging, and backplane dispatch.

20. The device of claim 15, wherein the second sub-operations performed by second processing segments are selected from the group consisting of:

backplane packet collection, organization of packets according to source or priority, and end-of-packet detection.

21. The device of claim 15, wherein the third sub-operations performed by third processing segments are selected from the group consisting of:

packet availability detection, ordered packet retrieval, forwarding identifier lookup, VLAN tag replacement, packet header processing for replacing MAC addresses, and VLAN tag insertion.