Network routing apparatus for enhanced efficiency and monitoring capability

• US 20090279558A1
• Filed: 05/06/2002
• Published: 11/12/2009
• Est. Priority Date: 05/06/2002
• Status: Abandoned Application

• Current Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Patel, Ronak, Davis, Ian Edward, Prince, Jeffrey A.
• Application Number:
  US10/140,749
• Publication Number:
  US 20090279558A1
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/39 Credit based
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Claims

1. A network device comprising:

a memory; and

a port controller coupled to the memory, the port controller comprising;

a packet input circuit;

a buffer manager circuit; and

a packet output circuit;

wherein the memory is located external to the port controller;

wherein the packet input circuit is configured to receive incoming data packets received by the network device, and to generate associated header information for each data packet by performing a lookup using information in a packet header of the data packet;

wherein the memory is configured to store the data packets after processing of the incoming data packets by the packet input circuit and to store information enabling lookups to be performed for the data packets;

wherein the buffer manager circuit is configured to

cause a lookup to be performed in the memory for each data packet using the information enabling lookups stored in the memory; and

wherein the packet output circuit is configured to receive the data packets stored in the memory and to assemble outgoing data packets from contents of the stored data packets and the associated header information generated for the data packets.

2. The network device of claim 1, wherein the port controller further comprises a rate shaper.

3. The network device of claim 1 wherein the port controller is implemented as an ASIC.

4. The network device of claim 1 wherein the port controller is implemented by programming a field programmable gate array.

5. The network device of claim 1, wherein the port controller is configured to interface with one or more gigabit Ethernet ports.

6. The network device of claim 1, wherein the port controller is configured to interface with one or more 10/100 megabit Ethernet ports.

7. The network device of claim 1, wherein the port controller is configured to interface with one or more packet over SONET ports.

8. The network device of claim 1, wherein the port controller is configured to interface with one or more ATM ports.

9. The network device of claim 1, wherein the packet input circuit further comprises a packet evaluation circuit.

10. The network device of claim 9, wherein the packet evaluation circuit comprises a content addressable memory (CAM) interface for looking up in a CAM processed packet information applicable to the incoming data packets.

11. The network device of claim 10, wherein the port controller comprises a parameter memory interface to a parameter memory containing parameter values applicable to the incoming data packets, wherein the looking up in the CAM returns an index to the parameter memory.

12. The network device of claim 11, wherein the parameter values are from a group consisting of switching parameters and routing parameters.

13. The network device of claim 10, wherein the packet evaluation circuit further comprises a port tracker circuit for decoding packet information for each incoming data packet.

14. The network device of claim 10, wherein the packet evaluation circuit includes a microprocessor for processing packet information from each incoming data packet and using the packet information to facilitate looking up in the CAM.

15. The network device of claim 14, wherein the microprocessor comprises a plurality of registers configured to store a portion of the packet information.

16. The network device of claim 15, wherein the port controller further comprises an arithmetic logic unit for operating on the packet information.

17. The network device of claim 16, wherein the port controller further comprises a register select circuit, configured to select the content of one of the registers to be an operand in the arithmetic logic unit.

18. The network device of claim 16, wherein the port controller further comprises a feedback select circuit configured to select an output value of an arithmetic unit to be an operand in the arithmetic logic unit.

19. The network device of claim 15, wherein the packet evaluation circuit further comprises a CAM lookup handler, configured to use the contents of the registers at a predetermined time point in a lookup request to the CAM.

20. The network device of claim 11, wherein the port controller further comprises a parameter memory handler.

21. The network device of claim 13, wherein the port tracker circuit identifies valid packet context in each incoming data packet.

22. The network device of claim 13, wherein the port tracker circuit removes a VLAN tag from the incoming data packets.

23. The network device of claim 13, wherein the port tracker circuit copies the VLAN tag to a packet status word.

24. The network device of claim 13, wherein the port tracker circuit performs TOS field lookups.

25. The network device of claim 14, wherein the microprocessor creates a packet header for each outgoing data packet.

26. The network device of claim 14, wherein the microprocessor comprises a RISC processor.

27. The network device of claim 1, wherein the packet input circuit comprises an 8B/10B decoder.

28. The network device of claim 1, wherein the packet input circuit further comprises a CRC verification logic circuit.

29. The network device of claim 1, wherein the packet input circuit further comprises an auto-negotiation logic circuit for connecting with network devices of various speeds.

30. The network device of claim 1, wherein the port controller further comprises a polling logic circuit configured to perform time slot polling of the input ports.

31. The network device of claim 30, wherein the port controller further comprises a data FIFO memory, configured to receive data packets from said polling logic circuit.

32. The network device of claim 1, wherein the port controller is configured to:

map an incoming data packet received over a port of the network device to a traffic class from one or more traffic classes associated with the port, each of the one or more traffic classes being independently controllable based upon programmable bandwidth limits, each traffic class having an associated total credit value indicative of a number of credits for the traffic class and associated value indicating a number of bytes corresponding to each credit; and

determine whether to forward or drop the received data packet based upon a total credit value associated with the traffic class to which the received data packet is mapped.

33. The network device of claim 1, wherein the port controller is configured to:

map an incoming packet received over a port of the network device to a traffic class from one or more traffic classes associated with the port based upon packet priority associated with the received data packet, each of the one or more traffic classes being independently controllable based upon programmable bandwidth limits, each traffic class having an associated total credit value indicative of a number of credits for the traffic class and an associated value indicating a number of bytes corresponding to each credit; and

determine whether to forward or drop the received data packet based upon a total credit value associated with the traffic class to which the received data packet is mapped.

34. The network device of claim 1, wherein the port controller is configured to:

map an incoming packet received over a port of the network device to a traffic class from one or more traffic classes associated with the port based upon IP/IPX address of the received packet, each of the one or more traffic classes being independently controllable based upon programmable bandwidth limits, each traffic class having an associated total credit value indicative of a number of credits for the traffic class and an associated value indicating a number of bytes corresponding to each credit; and

determine whether to forward or drop the received data packet based upon a total credit value associated with the traffic class to which the received data packet is mapped.

35. The network device of claim 2, wherein rate shaping is performed for input ports and output ports of the network device.

36. The network device of claim 1, wherein the port controller comprises an internal VLAN table.

37. The network device of claim 1, wherein said buffer manager circuit routes jumbo packets.

38. The network device of claim 1, wherein said buffer manager circuit routes multicast packets.

39. The network device of claim 2, wherein the buffer manager circuit creates a plurality of traffic classes based upon packet information in the incoming packets and performs rate shaping for the traffic classes.

40. The network device of claim 39, where the rate shaper comprises a credit counter for each traffic class, which is furnished with a count at predetermined interval and decremented in response to processing of each data packet of the traffic class.

41. The network device of claim 1, wherein the packet input circuit assigns a priority to each data packet.

42. The network device of claim 41, wherein the priority is determined from a VLAN priority specified in the data packet.

43. The network device of claim 41, wherein the priority is determined from a TOS priority specified in the data packet.

44. The network device of claim 41, wherein the priority is determined from a VLAN priority specified in the data packet and a TOS priority specified in the data packet.

45. The network device of claim 1, wherein the port controller is coupled to a plurality of ports, wherein each port is provided an media access controller (MAC) address of which a first group of bits are common among ports in the plurality of ports, and wherein a second group of bits of the MAC address are programmable.

46. The network device of claim 1, wherein the port controller further comprises an on-chip table for supporting virtual local area network (VLAN) functions.

47. The network device of claim 46, wherein the on-chip table specifies blocking of data packets on a per port basis.

48. The network device of claim 46, wherein forwarding of a VLAN tagged data packet is determined by a corresponding value stored in the on-chip table.

49. The network device of claim 46, wherein rate shaping of a port in the port controller associated with a VLAN is determined by an associated quality of service (QOS) entry in the on-chip table.

50. The network device of claim 1, wherein the buffer manager handles multicasting specified in a virtual local area network (VLAN) data packet.

51. The network device of claim 50, wherein the buffer manager handles multicasting specified in the VLAN data packet according to instructions associated with each transmit port.

52. The network device of claim 51, wherein the instructions are provided in a replacement table associated with the transmit port.

53. The network device of claim 1, wherein the buffer manager circuit is further configured to queue a first data packet from the data packets in a particular port queue from a plurality of port queues, the plurality of port queues corresponding to a plurality of ports of the network device, the particular port queue corresponding to a particular port from the plurality of ports to which the first data packet is to be forwarded.

54-57. -57. (canceled)