Backplane Interface Adapter

• US 20090279561A1
• Filed: 02/17/2009
• Published: 11/12/2009
• Est. Priority Date: 11/17/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Chang, Andrew, Patel, Ronak, Wong, Ming G.
• Granted Patent: US 7,978,702 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/153 ATM switching fabrics having parallel switch planes
• CPC Class Codes: H04L 49/1538 Cell slicing
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Claims

1. A backplane interface adapter comprising:

at least one receiver that receives input cells carrying packets of data;

at least one cell generator that generates encoded cells which include the packets of data from the input cells; and

at least one transmitter that transmits the generated cells to a switching fabric; and

wherein each input cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent.

4. The backplane interface adapter of claim 1,

wherein each cell generator distributes remaining bytes of packet data across one or more blocks in said first cell until an end of packet condition is reached or a maximum cell size is reached.

5. The backplane interface adapter of claim 4, wherein each cell generator further encodes an end cell with end of packet information that varies depending upon a set of end of packet conditions including whether the end of packet occurs at the end of an initial block, at the end of the initial block, within a subsequent block, at a block boundary, or at a cell boundary.

2. (canceled)

3. (canceled)

6. A backplane interface adapter comprising:

at least one receiver that receives input cells carrying packets of data;

at least one cell generator that generates encoded cells which include the packets of data from the input cells; and

at least one transmitter that transmits the generated cells to a switching fabric;

a plurality of send queues coupled between said at least one cell generator and said at least one transmitter, wherein said at least one cell generator stores said generated cells in said plurality of send queues; and

a switching fabric transmit arbitrator that arbitrates the order in which data stored in said send queues is sent by the at least one transmitter to the switching fabric, wherein each send queue stores a respective group of cells corresponding to a respective originating source packet processor and a destination slot identifier.

7. A backplane interface adapter for interfacing with a switching fabric of a network switch, the network switch for switching packets in a network, the backplane interface adapter comprising:

at least one receiver that serially receives cells from the switching fabric via a full duplex serial link;

at least one transmitter that serially transmits cells to the switching fabric via a full duplex serial link;

wherein each said full duplex serial link is capable of handling full duplex traffic of at least 2.5 gigabits/second, and wherein at least some of the cells comprise in-band state information and at least one byte of a said packet; and

further comprising a second receiver that receives processed said packets from an at least 10 gigabit per second Ethernet packet processor of the network switch.

8. The backplane interface adapter of claim 7, wherein said state information comprises a destination slot identifier or a source slot identifier.

9. The backplane interface adapter of claim 7, wherein said state information of a said cell received from the switching fabric comprises a source slot identifier.

10. The backplane interface adapter of claim 7, wherein said state information of a said cell transmitted to the switching fabric comprises a destination slot identifier.

11. The backplane interface adapter of claim 8, wherein the state information of the cell comprises payload state information that indicates a particular state of data in the cell.

12. The backplane interface adapter of claim 9, wherein the state information of the said cell received from the switching fabric comprises payload state information that indicates a particular state of data in the cell.

13. The backplane interface adapter of claim 10, wherein the state information of the said cell transmitted to the switching fabric comprises payload state information that indicates a particular state of data in the cell.

14. The backplane interface adapter of claim 7, wherein the state information comprises information that indicates a start of a packet.

15. The backplane interface adapter of claim 9, wherein the state information comprises information that indicates a start of a packet.

16. The backplane interface adapter of claim 10, wherein the state information comprises information that indicates a start of a packet.

17. The backplane interface adapter of claim 7, wherein the state information comprises information that indicates an end of a packet.

18. The backplane interface adapter of claim 9, wherein the state information comprises information that indicates an end of a packet.

19. The backplane interface adapter of claim 10, wherein the state information comprises information that indicates an end of a packet.