Signal Filtering Method and Electronic Device

• US 20090284466A1
• Filed: 01/07/2009
• Published: 11/19/2009
• Est. Priority Date: 05/16/2008
• Status: Active Grant

• Current Assignee: HTC Corporation
• Original Assignee: HTC Corporation
• Inventors: Chen, Hsi-Kun
• Granted Patent: US 8,207,938 B2
• Time in Patent Office: Days
• US Class Current: 345/157
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device

Abstract

A signal filtering method for filtering signals obtained at a number of time points by an electronic device is provided. Each of the signals corresponds to an i-th value at an i-th time point of the abovementioned time points, and the i-th value and an (i+1)-th value are defined as an i-th ordering sequence, wherein i is a positive integer. Each of the i-th ordering sequence and an (i+1)-th ordering sequence conforms to a first strict monotonicity. The method includes the following steps. Firstly, whether an (i+2)-th ordering sequence conforms to a second strict monotonicity is determined. If yes, then execute the next step. Determine whether an (i+3)-th ordering sequence conforms to the second strict monotonicity. If not, a signal obtained at an (i+3)-th time point is deleted.

Claims

1. A signal filtering method provided for filtering a plurality of signals obtained by an electronic device at a plurality of time points, wherein each of the signals obtained at an i-th time point of the above time points corresponds to an i-th value, the i-th value and an (i+1)-th value are defined as an i-th ordering sequence, i is a positive integer, each of the i-th ordering sequence and an (i+1)-th ordering sequence conforms to a first strict monotonicity, and the method comprises:

(a) determining whether an (i+2)-th ordering sequence conforms to a second strict monotonicity, and executing step (b) if the (i+2)-th ordering sequence conforms to the second strict monotonicity; and

(b) determining whether an (i+3)-th ordering sequence conforms to the second strict monotonicity, and deleting a signal obtained at an (i+3)-th time point if the (i+3)-th ordering sequence does not conform to the second strict monotonicity.

2. The method according to claim 1, wherein before the step (a), the method comprises:

(a0) determining whether the two values of the (i+2)-th ordering sequence are equal to each other, and deleting the signal obtained at the (i+3)-th time point if the two values of the (i+2)-th ordering sequence are equal to each other.

3. The method according to claim 1, wherein before the step (b), the method comprises:

(b0) determining whether the two values of the (i+3)-th ordering sequence are equal to each other, and deleting a signal obtained at an (i+4)-th time point if the two values of the (i+3)-th ordering sequence are equal to each other.

4. The method according to claim 1, wherein the step (a) comprises:

outputting the signals obtained at the (i+1)-th time point, the (i+2)-th time point, and the (i+3)-th time point if it is determined that the (i+2)-th ordering sequence does not conform to the second strict monotonicity.

5. The method according to claim 1, wherein the step (b) comprises:

outputting the signals obtained at the (i+1)-th time point, the (i+2)-th time point, and an (i+3)-th time point if it is determined that the (i+3)-th ordering sequence conforms to the second strict monotonicity.

6. The method according to claim 1, wherein the first strict monotonicity is one of strict monotonic increasing and strict monotonic decreasing, and the second strict monotonicity is the other one of strict monotonic increasing and strict monotonic decreasing.

7. An electronic device, comprising:

a fetching unit for fetching a plurality of signals obtained at a plurality of time points having an equal interval between two adjacent time points, wherein each of the signals obtained at an i-th time point of the above time points corresponds to an i-th value, the i-th value and an (i+1)-th value are defined as an i-th ordering sequence, i is a positive integer, and each of the i-th ordering sequence and an (i+1)-th ordering sequence conforms to a first strict monotonicity;

a determining unit for determining whether an (i+2)-th ordering sequence conforms to a second strict monotonicity, and for determining whether an (i+3)-th ordering sequence conforms to the second strict monotonicity; and

a filtering unit for filtering the signals obtained by the fetching unit, wherein if the determining unit determines that the (i+2)-th ordering sequence conforms to the second strict monotonicity but the determining unit determines that the (i+3)-th ordering sequence does not conform to the second strict monotonicity, then the filtering unit deletes a signal obtained at an (i+3)-th time point.

8. The device according to claim 7, wherein the determining unit is further for determining whether the two values of the (i+2)-th ordering sequence are equal to each other, and the filtering unit deletes the signal obtained at the (i+3)-th time point if the two values of the (i+2)-th ordering sequence are equal to each other.

9. The device according to claim 7, wherein the determining unit is further used for determining whether the two values of the (i+3)-th ordering sequence are equal to each other, and the filtering unit deletes a signal obtained at an (i+4)-th time point if the two values of the (i+3)-th ordering sequence are equal to each other.

10. The device according to claim 7, wherein if the determining unit determines that the (i+2)-th ordering sequence does not conform to the second strict monotonicity, the filtering unit outputs the signals obtained at the (i+1)-th time point, the (i+2)-th time point, and the (i+3)-th time point.

11. The device according to claim 7, wherein if the determining unit determines that the (i+3)-th ordering sequence conforms to the second strict monotonicity, the filtering unit outputs the signals obtained at the (i+1)-th time point, the (i+2)-th time point and an (i+3)-th time point.

12. The device according to claim 7, wherein the first strict monotonicity is one of strict monotonic increasing and strict monotonic decreasing, and the second strict monotonicity is the other one of strict monotonic increasing and strict monotonic decreasing.

13. The device according to claim 7, further comprising:

a display unit for displaying a frame; and

a controlling unit for determining a control mode according to the signals outputted from the filtering unit to control the content of the frame displayed by the display unit.

14. The device according to claim 7, wherein the frame has a cursor and the control mode is a direction mode used for controlling the cursor'"'"'s moving direction in the frame.

15. The device according to claim 14, wherein the frame is a one-dimensional frame and the direction mode is used for controlling the cursor to move forward or backward in the one-dimensional frame.

16. The device according to claim 14, wherein the frame is a two-dimensional frame and the direction mode is used for controlling the cursor'"'"'s coordinate in the two-dimensional frame.

17. The device according to claim 7, wherein the fetching unit comprises a sensing wheel for fetching the signals by way of sensing.

18. An electronic device used for an application program to filter a plurality of signals obtained at a plurality of time points having an equal interval between two adjacent time points, wherein each of the signals obtained at an i-th time point of the above time points corresponds to an i-th value, the i-th value and an (i+1)-th value are defined as an i-th ordering sequence, i is a positive integer, each of the i-th ordering sequence and an (i+1)-th ordering sequence conforms to a first strict monotonicity, and the electronic device comprises:

a memory for storing a programming code of an operating system; and

a processor used for reading and executing the programming code of the operating system and then executing the application program to filter the signals, wherein the processor is for determining whether an (i+2)-th ordering sequence conforms to a second strict monotonicity, and for determining whether an (i+3)-th ordering sequence conforms to the second strict monotonicity, and if the processor determined that the (i+2)-th ordering sequence conforms to the second strict monotonicity but the (i+3)-th ordering sequence does not conform to the second strict monotonicity, then the processor deletes a signal obtained at an (i+3)-th time point.

19. The electronic device according to claim 18, wherein the processor is further for determining whether the two values of the (i+2)-th ordering sequence are equal to each other, and deleting the signal obtained at the (i+3)-th time point if the two values of the (i+2)-th ordering sequence are equal to each other.

20. The electronic device according to claim 18, wherein the processor is further for determining whether the two values of the (i+3)-th ordering sequence are equal to each other, and deleting a signal obtained at an (i+4)-th time point if the two values of the (i+3)-th ordering sequence are equal to each other.

21. The electronic device according to claim 18, wherein the processor is further for outputting the signals obtained at the (i+1)-th time point, the (i+2)-th time point and the (i+3)-th time point if the processor determines that the (i+2)-th ordering sequence does not conform to the second strict monotonicity.

22. The electronic device according to claim 18, wherein the processor is further for outputting the signals obtained at the (i+1)-th time point, the (i+2)-th time point and an (i+3)-th time point if the processor determines that the (i+3)-th ordering sequence conforms to the second strict monotonicity.