Dual Stress Liner Device and Method

• US 20090289375A1
• Filed: 08/04/2009
• Published: 11/26/2009
• Est. Priority Date: 07/05/2006
• Status: Active Grant

• Current Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: SUDO, Gaku
• Granted Patent: US 8,004,035 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Claims

1. A semiconductor device, comprising:

a substrate;

first and second field-effect transistors formed on and in said substrate;

a tensile stress liner formed over the first field-effect transistor;

a compression stress liner formed over the second field-effect transistor; and

a conductive contact disposed between the first and second field-effect transistors, wherein a first side of said contact is adjacent to said tensile stress liner, an opposite second side of said contact is adjacent to said compression stress liner, and wherein said stress liners do not overlap.

2. The device of claim 1, wherein said stress liners are SiN stress liners.

3. The device of claim 1, further comprising a first insulating layer having a top surface at a height common with a top surface of one of said stress liners.

4. The device of claim 3, further comprising a second insulating layer formed on said first insulating layer.

5. The device of claim 4, wherein said contact is formed in a trench formed in said second insulating layer but not in said first insulating layer.

6. The device of claim 5, further comprising a second contact extending through both of said insulating layers and only one of said stress layers to reach one of said field-effect transistors.

7. The device of claim 1, wherein said contact is an interconnect contact that reaches an interconnect gate structure, and where said interconnect gate structure is above an isolation region of said substrate.