LOW DROPOUT REGULATOR
First Claim
1. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:
- a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain;
a compensation capacitor coupled between the gate and the drain of the compensation transistor;
a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source;
a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor; and
a source of bias current coupled to the source of the second compensation transistor.
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Accused Products
Abstract
The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles'"'"' frequency reshaping” are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance is needed to stabilize a regulator. LDO regulators, in system on chip application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications.
15 Citations
21 Claims
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1. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:
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a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain; a compensation capacitor coupled between the gate and the drain of the compensation transistor; a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source; a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor; and a source of bias current coupled to the source of the second compensation transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:
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a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain; a compensation capacitor coupled between the gate and the drain of the compensation transistor; a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source; a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor; and a source of bias current coupled to the source of the second compensation transistor and to the drain of the driver transistor.
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21. A stability compensation circuit for a low dropout regulator, the low dropout regulator including a driver transistor, the circuit comprising:
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a first compensation transistor having a gate coupled to a gate of the driver transistor, a source coupled to an unregulated input voltage, and a drain; a compensation capacitor coupled between the gate and the drain of the compensation transistor; a second compensation transistor having a gate coupled to a drain of the driver transistor, a drain coupled to the unregulated input voltage, and a source; a resistor coupled between the drain of the first compensation transistor and the source of the second compensation transistor; and a source of bias current coupled to the source of the second compensation transistor, the drain of the driver transistor, and to an error amplifier in the low dropout regulator.
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Specification