ELECTRICAL OVERSTRESS AND TRANSIENT LATCH-UP PULSE GENERATION SYSTEM, CIRCUIT, AND METHOD

• US 20090289636A1
• Filed: 05/23/2008
• Published: 11/26/2009
• Est. Priority Date: 05/23/2008
• Status: Active Grant

• Current Assignee: Thermo Keytek LLC (Thermo Fisher Scientific Incorporated)
• Original Assignee: Thermo Fisher Scientific Incorporated
• Inventors: Hernandez, Marcos
• Granted Patent: US 7,928,737 B2
• Time in Patent Office: Days
• US Class Current: 324/555
• CPC Class Codes: G01R 31/002 where the device under test is an electronic circuit
• CPC Class Codes: G01R 31/14 Circuits therefor , e.g. for generating test voltages, sensing circuits G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

A circuit arrangement, system, and method to test a device with a plurality of pins for electric overstress and transient induced latch-up characteristics. The circuit arrangement includes an inverting operational amplifier with a unity gain to receive a triggering signal and supply an inverted signal to a power amplifier. The power amplifier transforms the inverted signal into a test signal, which is received by a ratio circuit. The test signal is further operable to test the electric overstress and transient induced latch-up characteristics of the device. The ratio circuit transforms the test signal into a ratio signal. The ratio signal has a voltage magnitude that corresponds to the current magnitude of the test signal. The test signal and ratio signal are measured to determine if, during testing, the device or a component of the device has failed.

Claims

1. In a system to test a device, a pulse generation circuit operable to selectively apply a first test signal to test an electrical overstress characteristic of the device and a second test signal to test a transient induced latch-up characteristic of the device.

2. In the system of claim 1, the pulse generation circuit further operable to provide a ratio signal indicative of a current applied by the first or second test signal.

3. In the system of claim 1, the pulse generation circuit including an inverting operational amplifier with a unity gain to transform a triggering signal from the system into an inverted signal, a power amplifier to transform the inverted signal into the first or second test signal, and a ratio circuit to transform the first or second test signal into a ratio signal indicative of the current applied by the first or second test signal.

4. In the system of claim 3, the ratio circuit including a conditioning operational amplifier operable to transform the first or second test signal into the ratio signal.

5. In the system of claim 3, the ratio circuit including a first conditioning operational amplifier operable to transform the first or second test signal into a limited ratio signal and a second conditioning operational amplifier operable to transform the limited ratio signal into the ratio signal.

6. A circuit arrangement to produce a test signal and a ratio signal, the test signal used to test a device, the circuit comprising:

a trigger signal generation circuit operable to generate a triggering signal; and

a pulse generation circuit responsive to the triggering signal and operable to generate a test signal to be applied to the device and a ratio signal indicative of a current applied to the device by the test signal.

7. The circuit arrangement of claim 6, the pulse generation circuit including:

an inverting operational amplifier with a unity gain, the inverting operational amplifier operable to receive a triggering signal and transform the triggering signal into an inverted signal;

a power amplifier electrically coupled with the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test; and

a ratio circuit electrically coupled with the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal.

8. The circuit arrangement of claim 7, the ratio circuit including:

a conditioning operational amplifier operable to receive the test signal and transform the test signal into the ratio signal.

9. The circuit arrangement of claim 7, the ratio circuit including:

a first conditioning operational amplifier operable to receive the test signal and transform the test signal into a limited ratio signal; and

a second conditioning operational amplifier electrically coupled with the first conditioning operational amplifier, the second conditioning operational amplifier operable to receive the limited ratio signal and transform the limited ratio signal into the ratio signal.

10. The circuit arrangement of claim 6, the test signal used to test a transient induced latch-up or an electrical overstress characteristic of the device.

11. A circuit arrangement to produce a test signal and a ratio signal, the test signal used to test a device, the circuit comprising:

an inverting operational amplifier with a unity gain, the inverting operational amplifier operable to receive a triggering signal and transform the triggering signal into an inverted signal;

a power amplifier electrically coupled with the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test signal, the test signal used to test at least one of a transient induced latch-up or an electrical overstress characteristic of the device; and

a ratio circuit electrically coupled with the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal, the ratio signal such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal.

12. The circuit arrangement of claim 11, wherein a DC voltage of the test signal produced by the pulse generation circuit is from about positive thirty volts to about negative thirty volts.

13. The circuit arrangement of claim 11, wherein a length of the test signal is from about twenty microseconds to about one millisecond.

14. The circuit arrangement of claim 11, wherein the circuit arrangement is operable to produce test signal to test the transient induced latch-up characteristic of the device for a range of about nineteen microseconds to about twenty-one microseconds.

15. The circuit arrangement of claim 11, wherein the circuit arrangement is operable to produce the test signal to test the electrical overstress characteristic of the device for a range of about 750 microseconds to about 780 microseconds.

16. The circuit arrangement of claim 11, wherein the ratio circuit comprises:

a conditioning operational amplifier operable to receive the test signal and transform the test signal into the ratio signal.

17. The circuit arrangement of claim 11, wherein the ratio circuit comprises:

a first conditioning operational amplifier operable to receive the test signal and transform the test signal into a limited ratio signal; and

a second conditioning operational amplifier electrically coupled with the first conditioning operational amplifier, the second conditioning operational amplifier operable to receive the limited ratio signal and transform the limited ratio signal into the ratio signal.

18. A system to test a transient induced latch-up or an electrical overstress characteristic of a device of the type that includes a plurality of pins, the system comprising:

a pulse generation circuit operable to produce a test signal and a ratio signal, the pulse generation circuit including an inverting operational amplifier having a unity gain and electrically coupled with a digital-to-analog converter, the inverting operational amplifier operable to receive a triggering signal from the digital-to-analog converter and transform the triggering signal into an inverted signal, a power amplifier electrically coupled to the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test signal, and a ratio circuit electrically coupled to the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal, the ratio signal such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal;

a relay pin matrix electrically coupled to the pulse generation circuit, the relay pin matrix operable to receive the test signal and the device, the relay pin matrix programmatically controlled to relay the test signal to at least one pin from among the plurality of pins of the device to test the transient induced latch-up or electrical overstress characteristic of the device;

an oscilloscope electrically coupled with the pulse generation circuit, the oscilloscope operable to measure the test signal and the ratio signal; and

a controller electrically coupled to the analog-to-digital converter, oscilloscope, and relay pin matrix, the controller operable to interface with the oscilloscope and store the measured test signal and ratio signal, the controller operable to programmatically control the relay pin matrix to relay the test signal to the at least one pin from among the plurality of pins of the device, the controller operable to provide an analog triggering signal to be converted into the triggering signal by the analog-to-digital converter.

19. The system of claim 18, wherein the ratio circuit further comprises:

a conditioning operational amplifier operable to receive the test signal and transform the test signal into the ratio signal.

20. The system of claim 18, wherein the ratio circuit further comprises:

a first conditioning operational amplifier operable to receive the test signal and transform the test signal into a limited ratio signal; and

a second conditioning operational amplifier electrically coupled with the first conditioning operational amplifier, the second conditioning operational amplifier operable to receive the limited ratio signal and transform the limited ratio signal into the ratio signal.

21. The system of claim 18, wherein the controller is further operable to create a test plan for testing of the transient induced latch-up or electrical overstress characteristic of the device.

22. The system of claim 18, wherein the controller is further operable to provide an indication in response to detecting an abnormal test signal or an abnormal ratio signal.

23. The system of claim 18, wherein a DC voltage of the test signal produced by the pulse generation circuit is from about positive thirty volts to about negative thirty volts.

24. The system of claim 18, wherein a length of the test signal is from about twenty microseconds to about one millisecond.

25. The system of claim 18, wherein the pulse generation circuit is operable to produce the test signal to test the transient induced latch-up characteristic of the device for a range of about nineteen microseconds to about twenty-one microseconds.

26. The system of claim 18, wherein the pulse generation circuit is operable to produce the test signal to test the electrical overstress characteristic of the device for a range of about 750 microseconds to about 780 microseconds.

27. A method of testing a device of the type that includes a plurality of pins with a system comprising a pulse generation circuit, a relay pin matrix, an oscilloscope, and a controller, wherein the pulse generation circuit is electrically coupled with the relay pin matrix, oscilloscope, and controller, and wherein the controller is electrically coupled with the relay pin matrix and oscilloscope, the method comprising:

programmatically controlling the relay pin matrix with the controller to relay a signal from the pulse generation circuit to at least one pin from among the plurality of pins of the device;

producing a triggering signal with the controller;

transforming the triggering signal into a test signal and a ratio signal with the pulse generation circuit, wherein the test signal is operable to test at least one of a transient induced latch-up or an electrical overstress characteristic of the device, transforming the triggering signal into the test signal and the ratio signal further comprising;

converting the triggering signal with an analog-to-digital converter,

receiving the converted triggering signal at the pulse generation circuit,

transforming the triggering signal into an inverted signal with an inverting operational amplifier having a unity gain in the pulse generation circuit,

transforming the inverted signal into the test signal with the power amplifier electrically coupled with the inverting operational amplifier, wherein the test signal is the signal relayed to the at least one pin of the device, and

transforming the test signal into the ratio signal with a ratio circuit electrically coupled with the power amplifier in the pulse generation circuit, wherein the ratio signal is such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal;

measuring the test signal and the ratio signal with the oscilloscope during the testing;

in response to relaying the test signal to at least one pin of the device and measuring the ratio signal, determining at least one of the transient induced latch-up or electrical overstress characteristic of the device.

28. The method of claim 27, wherein the ratio circuit includes a conditioning operational amplifier operable to receive the test signal and transform the test signal into the ratio signal.

29. The system of claim 27, wherein the ratio circuit includes a first conditioning operational amplifier operable to receive the test signal and transform the test signal into a limited ratio signal, and a second conditioning operational operable to receive the limited ratio signal and transform the limited ratio signal into the ratio signal.

30. A method of selectively configuring a pulse generation circuit to output a test signal to test a transient induced latch-up or electrical overstress characteristic of a device of the type that includes a plurality of pins, the method comprising:

producing a triggering pulse with a controller;

transforming the triggering pulse into the test signal and a ratio signal with the pulse generation circuit, the pulse generation circuit electrically coupled with the controller and the device; and

testing the device with the test signal.

31. The method of claim 30, further comprising:

measuring the test signal and the ratio signal with an oscilloscope, the oscilloscope electrically coupled with the pulse generation circuit and the controller; and

analyzing the measured test signal and ratio signal to determine the transient induced latch-up or electrical overstress characteristic of the device.

32. The method of claim 30, further comprising:

transforming the triggering pulse into an analog triggering signal with an analog-to-digital converter electrically coupled with the controller and the pulse generation circuit.

33. The method of claim 32, wherein the pulse generation circuit includes an inverting operational amplifier having a unity gain, the inverting operational amplifier operable to receive the analog triggering signal from the digital-to-analog converter and transform the analog triggering signal into an inverted signal, a power amplifier electrically coupled to the inverting operational amplifier, the power amplifier operable to receive the inverted signal and transform the inverted signal into the test signal, and a ratio circuit electrically coupled to the power amplifier, the ratio circuit operable to receive the test signal and transform the test signal into the ratio signal, the ratio signal such that the magnitude of the voltage of the ratio signal substantially corresponds to the magnitude of the current of the test signal.

34. The method of claim 33, wherein the ratio circuit includes a conditioning operational amplifier operable to receive the test signal and transform the test signal into the ratio signal.

35. The method of claim 33, wherein the ratio circuit includes a first conditioning operational amplifier operable to receive the test signal and transform the test signal into a limited ratio signal, and a second conditioning operational amplifier electrically coupled with the first conditioning operational amplifier, the second conditioning operational amplifier operable to receive the limited ratio signal and transform the limited ratio signal into the ratio signal.