FAST TURN ON ACTIVE DCAP CELL

• US 20090295470A1
• Filed: 05/29/2008
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Cao, Lihui, Rong, Peng
• Granted Patent: US 7,705,654 B2
• Time in Patent Office: Days
• US Class Current: 327/551
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents.

Claims

1. A fast active DCAP cell connected to a first rail and to a second rail, said fast active DCAP cell comprising:

a first NMOS transistor having its drain and source connected to the first rail, and a first PMOS transistor having its drain and source connected to the second rail, wherein the gate of the first NMOS transistor is connected to the drain of a second PMOS transistor and to the drain of a third PMOS transistor, and the second and third PMOS transistors have their sources connected to the second rail, and wherein the gate of the first PMOS transistor is connected to the drain of a second NMOS transistor and to the drain of a third NMOS transistor, and the second and third NMOS transistors have their sources connected to the first rail.

2. A fast active DCAP cell as recited in claim 1, wherein none of the gates of the transistors are connected directly to the rails.

3. A fast active DCAP cell as recited in claim 1, wherein the gate of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the third PMOS transistor are connected to the gate of the second NMOS transistor.

4. A fast active DCAP cell as recited in claim 1, wherein the gate of the first PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the gate of the second PMOS transistor.

5. A fast active DCAP cell as recited in claim 1, wherein the gate of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the third PMOS transistor are connected to the gate of the second NMOS transistor, and wherein the gate of the first PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the gate of the second PMOS transistor.

6. A fast active DCAP cell as recited in claim 1, wherein the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor.

7. A fast active DCAP cell connected to a first rail and to a second rail, said fast active DCAP cell comprising:

a first NMOS transistor, a second NMOS transistor and a third NMOS transistor;

a first PMOS transistor, a second PMOS transistor and a third PMOS transistor;

wherein the first NMOS transistor has its drain and source connected to the first rail, and has its gate connected to the drain of the second and third PMOS transistors, said second and third PMOS transistors having their sources connected to the second rail;

wherein the first PMOS transistor has its drain and source connected to the second rail, and has its gate connected to the drain of the second and third NMOS transistors, said second and third NMOS transistors having their sources connected to the first rail;

wherein the gate of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the third PMOS transistor are connected to the gate of the second NMOS transistor;

wherein the gate of the first PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the gate of the second PMOS transistor; and

wherein none of the gates of the transistors are connected directly to the rails.

8. A fast active DCAP cell connected to a first rail and to a second rail, said fast active DCAP cell comprising:

a first NMOS transistor, a second NMOS transistor and a third NMOS transistor;

a first PMOS transistor, a second PMOS transistor and a third PMOS transistor;

wherein the first NMOS transistor has its drain and source connected to the first rail, and has its gate connected to the drain of the second and third PMOS transistors, said second and third PMOS transistors having their sources connected to the second rail;

wherein the first PMOS transistor has its drain and source connected to the second rail, and has its gate connected to the drain of the second and third NMOS transistors, said second and third NMOS transistors having their sources connected to the first rail;

wherein the gate of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the third PMOS transistor are connected to the gate of the second NMOS transistor;

wherein the gate of the first PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the gate of the second PMOS transistor; and

wherein the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor.

9. A fast active DCAP cell as recited in claim 8, wherein none of the gates of the transistors are connected directly to the rails.