HYBRID MEMORY MANAGEMENT

• US 20090300269A1
• Filed: 05/28/2008
• Published: 12/03/2009
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Radke, William H., Murray, Michael, Furuhjelm, Martin Ragnar, Geldman, John
• Granted Patent: US 8,060,719 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Claims

1. A method for managing data stored on a memory device comprising a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining usage associated with a logical address of the memory device; and

at least partially based on the usage, storing data associated with the logical address in one of the first array and second array of memory cells.

2. The method of claim 1, wherein the first array of memory cells are single level memory cells (SLC) and the second array of memory cells are multi-level memory cells (MLC).

3. The method of claim 1, wherein the first array of memory comprises MLC memory cells configured to store a first number of bits per memory cell and the second array of memory comprises MLC memory cells configured to store a second number of bits per memory cell, and wherein the second number is greater than the first number.

4. The method of claim 1, further comprising storing the usage associated with logical addresses of the memory device in a usage table of the memory device.

5. The method of claim 4, wherein part or all of the usage table may be cleared in response to a received command from a host coupled to the memory device.

6. The method of claim 4, further comprising maintaining the usage associated with the logical address wherein maintaining the usage associated with the logical address comprises updating the usage table in response to a write operation performed for the logical address.

7. The method of claim 4, wherein the usage comprises a time stamp corresponding to a most recent occurrence of a write operation performed for the logical address.

8. The method of claim 4, wherein usage comprises a number of write operations performed for the logical address.

9. The method of claim 1, wherein storing data further comprises associating a logical address with a physical location in one of the first memory array and the second memory array in which the data is to be stored.

10. The method of claim 1, wherein determining usage comprises predicting future usage.

11. The method of claim 1, further comprising initially storing the data in the second memory array.

12. The method of claim 11, further comprising moving data stored in the second memory array to the first memory array based at least in part on usage associated with the logical address.

13. The method of claim 1, further comprising initially storing data in the first memory array.

14. The method of claim 1, wherein determining usage comprises determining if a logical address is accessed during a particular time period following power up of the memory device.

15. A non-volatile memory device having physical storage locations associated with logical addresses, and wherein the logical addresses are associated with data, the memory device comprising:

a first array of memory cells each memory cell having a first density;

a second array of memory cells each memory cell having a second density; and

a controller, wherein the controller is configured to selectively perform a write operation on the first array of memory cells or on the second array of memory cells and to assign the logical addresses to the physical storage locations based at least partially on a number of write operations performed on each logical address, and to re-assign logical addresses to the first array of memory cells if the number of write operations exceeds a threshold value.

16. The memory device of claim 15, wherein the control circuitry is further configured to write data to the first array of memory cells or to the second array of memory cells at least partially in response to a received command from a host coupled to the control circuitry of the memory device.

17. The memory device of claim 15, wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data associated with a logical address having a lowest number of write operations performed on it to the second array of memory cells or by moving data associated with a logical address which has not had a write operation performed to it for longer than a particular period to the second array of memory cells.

18. The memory device of claim 15, wherein the control circuitry is further configured to move data associated with a logical address stored in the second array of memory cells to the first array of memory cells at least partially in response to the number of write operations performed on the logical address exceeding a threshold value.

19. An electronic system comprising:

a host that generates memory device control signals; and

a memory device, coupled to the host and configured to receive the memory device control signals, the memory device comprising;

a first array of memory cells each memory cell having a first density;

a second array of memory cells each memory cell having a second density; and

control circuitry, wherein the control circuitry is configured to store data in the first array of memory cells or the second array of memory cells based on interpreting a tracked history of received write operations issued to logical addresses of said data.

20. The electronic system of claim 19, wherein the data is stored in the first array of memory cells or the second array of memory cells in response to a command generated by the host and received by the memory device.

21. The electronic system of claim 20, wherein the command generated by the host is generated in response to an anticipated frequency of write operations to be performed on data to be stored in the memory device.

22. The electronic system of claim 19, wherein the control circuitry is further configured to move data corresponding to a logical address from the second array of memory cells to the first array of memory cells in response to exceeding a threshold number of write operations performed on the logical address.

23. The electronic system of claim 19, wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells.

24. The electronic system of claim 23, wherein the control circuitry is further configured to move data corresponding to a logical address mapped to the first array of memory cells and having a least number of write operations performed with respect to all logical block addresses mapped to the first array of memory cells to the second array of memory cells in order to maintain at least the particular number of spare logical address locations in the first array of memory cells.

25. The electronic system of claim 19, wherein the host is configured to perform a boot load operation.

26. The electronic system of claim 25, wherein the control circuitry is further configured to store data in the first array of memory cells or the second array of memory cells based at least in part on if the logical address associated with the data is accessed during the boot load operation.

27. A method for managing data stored on a memory device having a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining a nature of data to be associated with a logical location in memory; and

at least partially based on the nature, storing the data in one of the first array of memory cells and the second array of memory cells.

28. The method of claim 27, wherein the nature of the data is a frequency of usage of the data.

29. The method of claim 27, wherein the nature of the data is at least partially based on if the data is accessed during a particular time frame following power up of the memory device.

30. The method of claim 29, wherein the particular time frame corresponds to a duration of a boot load operation.

31. A memory device comprising:

a first array of memory cells each memory cell having a first density;

a second array of memory cells each memory cell having a second density; and

control circuitry, wherein the control circuitry is configured to determine usage data of a logical address in the memory device and store data associated with the logical address in one of the first array and second array of memory cells at least partially based on the usage.

32. The memory device of claim 31, wherein the usage data comprises a number of write operations that have been performed on the logical address.

33. The memory device of claim 32, wherein the usage data comprises a time stamp indicating when a most recent write operation on the logical address occurred.

34. The memory device of claim 31, wherein the control circuitry is further configured to perform a wear leveling operation on the first and second array of memory cells.

35. The memory device of claim 31, wherein the usage data comprises data such that time that has elapsed since a most recent write operation was performed on the logical address can be determined from the usage data.

36. An electronic system comprising:

a host having a hard disk drive interface utilizing a hard disk drive protocol for interfacing with a hard disk drive having solid state memory and magnetic media memory;

a memory device configured to emulate a hard disk drive and coupled to the host at least in part through the hard disk drive interface, the memory device comprising;

a first array of memory cells wherein each memory cell has a first density;

a second array of memory cells wherein each memory cell has a second density; and

control circuitry configured to store data indicated by the host to be stored in the solid state memory of a hard disk drive in the first array of memory cells and store data indicated by the host to be stored in the magnetic media of a hard disk drive in the second array of memory cells;

wherein the first density is less than the second density.

37. The electronic system of claim 36, wherein the first array of memory cells are single level memory cells (SLC) and the second array of memory cells are multi-level memory cells (MLC).

38. The electronic system of claim 36, wherein the first array of memory cells comprises MLC memory cells configured to store a first number of bits per memory cell and the second array of memory cells comprises MLC memory cells configured to store a second number of bits per memory cell, and wherein the second number of bits is greater than the first number of bits.

39. The electronic system of claim 36, wherein the control circuitry is further configured to pin a logical address to one of the first array of memory cells and the second array of memory cells in response to a command provided by the host.

40. The electronic system of claim 36, wherein the control circuitry is further configured to output a size of the first array of memory cells and a size of the second array of memory cells in response to a request by the host.