PACKAGE SUBSTRATE HAVING EMBEDDED SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF

• US 20090309202A1
• Filed: 06/12/2009
• Published: 12/17/2009
• Est. Priority Date: 06/13/2008
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Phoenix Precision Technology Corporation (Unimicron Technology Corporation)
• Inventors: Hsu, Shin-Ping, Chia, Kan-Jung
• Granted Patent: US 7,973,397 B2
• Time in Patent Office: Days
• US Class Current: 257/680
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0108 Transparent
• CPC Class Codes: H05K 2201/10121 Optical component, e.g. opto-electronic component
• CPC Class Codes: H05K 2203/1147 Sealing or impregnating, e.g. of pores
• CPC Class Codes: H05K 3/281 by means of a preformed insulating foil H05K3/284 takes precedence

Abstract

A packaging substrate having a semiconductor chip embedded and a fabrication method thereof are provided. The method includes forming a semiconductor chip in a through cavity of a core board and exposing a photosensitive portion of the semiconductor chip from the through cavity; sequentially forming a first dielectric layer and a first circuit layer on the core board, the first circuit layer being electrically connected to the electrode pads of the semiconductor chip; forming a light-permeable window on the first dielectric layer to expose the photosensitive portion of the semiconductor chip and adhering a light-permeable layer onto the light-permeable window, thereby permitting light to penetrate through the light-permeable layer to reach the photosensitive portion. Therefore, when fabricated with the method, the packaging substrate dispenses with conductive wires and dams and thus can be downsized.

Claims

1. A packaging substrate having an embedded semiconductor chip, comprising:

a core board having a first surface and an opposite second surface, and a through cavity penetrating the first and second surfaces;

the embedded semiconductor chip disposed in the through cavity and having an active surface and an opposite inactive surface, the active surface having a photosensitive portion and a plurality of electrode pads and being at a same side as the first surface of the core board, while the inactive surface being at a same side as the second surface of the core board;

a first dielectric layer formed on the active surface and the first surface of the core board, the first dielectric layer having a light-permeable window to expose the photosensitive portion of the embedded semiconductor chip;

a first circuit layer formed on the first dielectric layer and having a plurality of first conductive vias disposed in the first dielectric layer for electrically connecting to the electrode pads;

a second dielectric layer formed on the inactive surface and the second surface of the core board;

a second circuit layer formed on the second dielectric layer; and

a plurality of conductive through holes penetrating the core board and the first and second dielectric layers, and electrically connecting the first and second circuit layers.

2. The packaging substrate having an embedded semiconductor chip of claim 1, wherein an adhesive fills the gap between the walls of the through cavity and the semiconductor chip.

3. The packaging substrate having an embedded semiconductor chip of claim 1, further comprising an adhesive layer and a light-permeable layer, the adhesive layer being disposed on the first dielectric layer and the first circuit layer, and the light-permeable layer being disposed on the adhesive layer to seal the light-permeable window.

4. The packaging substrate having an embedded semiconductor chip of claim 3, wherein the light-permeable layer is made of glass.

5. The packaging substrate having an embedded semiconductor chip of claim 1, further comprising a solder mask layer disposed on the second dielectric layer and the second circuit layer and having a plurality of openings to expose portions of the second circuit layer to serve as conductive pads.

6. The packaging substrate having an embedded semiconductor chip of claim 1, further comprising a built-up structure disposed on the second dielectric layer and the second circuit layer and having at least a third dielectric layer, a third circuit layer disposed on the third dielectric layer, and a plurality of second conductive vias electrically connecting the second circuit layer and the third circuit layer, wherein a solder mask layer is formed on the built-up structure, the solder mask layer having a plurality of openings to expose portions of the outermost third circuit layer to serve as conductive pads.

7. A method for fabricating a packaging substrate structure having an embedded semiconductor chip, comprising:

providing a core board having a first surface and an opposite second surface, wherein the core board has a through cavity penetrating the first and the second surface;

providing a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has a photosensitive portion and a plurality of electrode pads, fixing the semiconductor chip into the through cavity, such that the active surface is exposed from the first surface of the core board and the inactive surface is exposed from the second surface of the core board;

forming a first dielectric layer on the first surface of the core board and the active surface, forming a second dielectric layer on the second surface of the core board and the inactive surface, also forming a plurality of through holes penetrating the core board and the first and second dielectric layers, wherein the first dielectric layer has a plurality of vias to expose the electrode pads;

forming a first circuit layer on the first dielectric layer, forming a second circuit layer on the second dielectric layer, also forming a plurality of first conductive vias in the vias to electrically connect the first circuit layer and the electrode pads, further forming a plurality of conductive through holes in the through holes to electrically connect the first circuit layer and the second circuit layer; and

forming a light-permeable window in the first dielectric layer to expose the photosensitive portion.

8. The method of claim 7, wherein the method for fabricating the first circuit layer, the second circuit layer, the first conductive vias, and the conductive through holes comprises:

forming a conductive seed-layer on the first and the second dielectric layers, walls of the vias, and walls of the through holes;

forming a resist layer on the conductive seed-layer on the first and the second dielectric layers, and forming a plurality of open areas in the resist layers to expose the conductive seed-layer on the walls of the vias, the walls of through holes, and portions of the first and the second dielectric layers;

forming a plurality of conductive through holes in the through holes, forming a first circuit layer on the first dielectric layer in the open areas, forming a plurality of first conductive vias in the vias, and forming a second circuit layer on the second dielectric layer in the open areas through the conductive seed-layer by electroplating; and

removing the resist layers and the conductive seed-layer covered by the resist layers.

9. The method of claim 7, wherein an adhesive fills the gap between the walls of the through cavity and the semiconductor chip to fix the semiconductor chip in the through cavity.

10. The method of claim 7, further comprising forming an adhesive layer on the first circuit layer and the first dielectric layer, and attaching a light-permeable layer onto the adhesive layer to seal the light-permeable window.

11. The method of claim 10, wherein the light-permeable layer is made of glass.

12. The method of claim 7, further comprising forming a solder mask layer on the second dielectric layer and the second circuit layer, and forming a plurality of openings in the solder mask layer to expose portions of the second circuit layer to serve as conductive pads.

13. The method of claim 7, further comprising forming a built-up structure on the second dielectric layer and the second circuit layer, wherein the built-up structure has at least a third dielectric layer, a third circuit layer disposed on the third dielectric layer, and a plurality of second conductive vias electrically connecting the second circuit layer to the third circuit layer, wherein a plurality of openings are formed in the solder mask layer to expose portions of the outermost third circuit layer to serve as conductive pads.