DEMODULATION CIRCUIT FOR ASK CODED OR AMPLITUDE MODULATED SIGNALS AS WELLS AS NFC AND RFID DEVICES COMPRISING THE SAME

• US 20090309652A1
• Filed: 01/15/2008
• Published: 12/17/2009
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Kranabenter, Helmut
• Granted Patent: US 7,907,005 B2
• Time in Patent Office: Days
• US Class Current: 329/347
• CPC Class Codes: H03D 1/22 Homodyne or synchrodyne circuits receiver circuits H04B1/30
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

Conventional modulation envelope demodulators for amplitude modulated signals (e.g. ASK coded signals RX) contain rectifier elements which extract a baseband signal BB. Disadvantageously, due to a non-linear characteristic of the rectifier elements, an amplitude of the baseband signal BB depends on an amplitude of the high-frequent carrier signal. The present invention discloses an improved demodulation circuit for demodulating of ASK coded or amplitude modulated signals. This is achieved by using a sampling mixer 4 and a phase adjusting regulation loop (5) by means of which the sampling of the ASK coded signal RX at its maxima is performed with high accuracy. Due to the absence of any rectifying elements, the baseband signal BB can be fully extracted from the ASK coded signals RX.

Claims

1. A demodulation circuit for ASK coded or amplitude modulated signals comprising:

a circuit input being adapted to receive an ASK coded or AM signal comprising a carrier signal being ASK coded according to a base band signal or amplitude modulated;

a first sampling mixer having a sampling signal input connected to the circuit input to receive the ASK coded or AM signal, a sampling clock input being adapted to receive a first sampling clock signal that defines first sampling points at which the ASK coded or AM signal when being present at the sampling signal input is sampled, and a sampling signal output being adapted to output the sampled signal;

signal shaping means having a signal input connected to the circuit input and being adapted to provide a recovered clock signal at an output thereof;

signal delay means being adapted to receive the recovered clock signal and to variably delay the recovered clock signal according to a delay control signal at a delay control input of the signal delay means, thereby generating a delayed recovered clock signal at an output thereof, wherein the delayed recovered clock signal is provided as the first sampling clock signal to the sampling clock input of the first sampling mixer; and

amplitude maximum detection means being adapted to detect if the first sampling points of the first sampling mixer correspond to respective amplitude maxima of the signal being sampled and to generate the delay control signal being indicative for deviations in time of the first sampling points from said amplitude maxima, wherein the delay control signal is fed to the delay control input of the signal delay means to increase or decrease the delay added to the recovered clock signal in order to adjust the delayed recovered clock signal such that the first sampling points are set to the amplitude maxima of the signal being sampled by the first sampling mixer.

2. A demodulation circuit as claimed in claim 1, wherein the signal shaping means are adapted to convert the ASK coded or AM signals into a rectangular recovered clock signal.

3. A demodulation circuit as claimed in claim 2, wherein the signal shaping means are configured as a limiting amplifier.

4. A demodulation circuit as claimed in claim 1, wherein the signal delay means are integrated in the signal shaping means.

5. A demodulation circuit as claimed in claim 1, wherein the signal shaping means are adapted to variably delay the recovered clock signal according to a delay control signal generated by the amplitude maximum detection means wherein the delay control signal is indicative for deviations in time of the first sampling points from said amplitude maxima, for increasing or decreasing the delay added to the recovered clock signal in order to adjust the delayed recovered clock signal such that the first sampling points are set to the amplitude maxima of the signal being sampled by the first sampling mixer.

6. A demodulation circuit as claimed in claim 1, wherein the frequency of the first sampling clock signal is substantially equal to that of the carrier frequency of the ASK coded or AM signal.

7. A demodulation circuit as claimed in claim 1, wherein the signal delay means are configured as voltage or current controlled signal delay means, wherein the delay control input thereof is adapted to receive a DC voltage or current as a delay control signal.

8. A demodulation circuit as claimed in claim 1, wherein the amplitude maximum detection means comprise:

a second sampling mixer having a sampling signal input connected to the circuit input to receive the ASK coded or AM signal, a sampling clock input being adapted to receive a second sampling clock signal that defines second sampling points at which the ASK coded or AM signal when being present at the sampling signal input is sampled, and a sampling signal output being adapted to output the sampled signal,

clock generation means for generating the second sampling clock signal having such a phase shift (Φ

) in respect of the first sampling clock signal that the second sampling clock signal defines second sampling points corresponding to zero-crossings of the signal being sampled when the first sampling points correspond to respective amplitude maxima of the signal being sampled,

and zero detection means being adapted to detect if the second sampling points of the second sampling mixer correspond to zero-crossings of the signal being sampled and to generate a delay control signal being indicative for deviations in time of the second sampling points from said zero-crossings,

wherein the delay control signal is fed to the delay control input of the signal delay means to increase or decrease the delay added to the recovered clock signal in order to adjust the delayed recovered clock signal such that the second sampling points are set to the zero crossings of the signal being sampled by the second sampling mixer.

9. A demodulation circuit as claimed in claim 8, wherein the phase shift between the first sampling clock signal and the second sampling clock signal is fixed to 90°

.

10. A demodulation circuit as claimed in claim 8, wherein the zero detection means are configured as a differential amplifier having a first input connected to the output of the second sampling mixer and a second input connected to ground.

11. A demodulation circuit as claimed in claim 1, wherein the first sampling mixer or the second sampling mixer are configured as fullwave mixers comprising a first sampling channel and a second sampling channel having outputs that are configured as differential outputs wherein the first sampling channel is controlled by the first sampling clock signal or the second sampling clock signal, respectively, and the second sampling channel is controlled by an inverted sampling clock signal of the first or the second sampling clock signal, thereby defining third sampling points and/or fourth sampling points that are phase shifted by 180°

degrees to the first sampling clock signal or the second sampling clock signal, respectively.

12. An NFC device, comprising a demodulation circuit according to claim 1.

13. An RFID transponder, comprising a demodulation circuit according to claim 1.