METHOD AND APPARATUS FOR VECTOR EXECUTION ON A SCALAR MACHINE

• US 20090313458A1
• Filed: 08/20/2009
• Published: 12/17/2009
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Colavin, Osvaldo, Rizzo, Davide, Soni, Vineet
• Granted Patent: US 8,935,515 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Claims

1-20. -20. (canceled)

21. A processor comprising:

a) an instruction decode circuit having an address output;

b) a rename circuit having an address input coupled to the address output of the instruction decode circuit and an address output, the rename circuit comprising;

i) a counter;

ii) an arithmetic circuit having a first input coupled to the address input and a second input coupled to the counter and a renamed output, the arithmetic circuit configured to provide at the renamed output a value representing a value at the first input offset by an amount proportional to a value at the second input;

iii) a switching circuit having a first input coupled to the address input, a second input coupled to the renamed output of the arithmetic circuit, a control input and an output coupled to the address output of the rename circuit, the switching circuit configured to couple a value at the first input of the switching circuit or a value at the second input of the switching circuit to the output selectively in response to a value of the control input; and

c) a data access circuit, having an address input coupled to the address output of the rename circuit.

22. The processor of claim 21, additionally comprising a plurality of output lines and instruction execution circuitry, the instruction execution circuitry controlling the values on the plurality of output lines.

23. A portable electronic device comprising:

a) a processor according to claim 22;

b) a user interface having a data input coupled to the output lines of the processor.

24. The processor of claim 21, additionally comprising a register file having a plurality of storage locations each having an address associated therewith and wherein the data access circuit is configured to access a storage location in the register file at an address specified by the value at the address input of the data access circuit.

25. The processor of claim 24, wherein the register file comprises a predetermined number of locations and the arithmetic circuit is configured to provide at the renamed output a value representing a value at the first input of the arithmetic circuit offset by an amount proportional to a value at the second input of the arithmetic circuit using modular arithmetic with a modulus less than the predetermined number of locations in the register file.

26. The processor of claim 25, additionally comprising an upper bound register storing a value representative of an address in the register file and the arithmetic circuit is configured to provide at the renamed output a value representing a value at the first input of the arithmetic circuit offset by an amount proportional to a value at the second input of the arithmetic circuit using modular arithmetic with a modulus equal to the value in the upper bound register.

27. The processor of claim 26, wherein the rename circuit additionally comprises control logic having a first input coupled to the upper bound register and a second input coupled to the address input of the rename circuit and an output coupled to the control input of the switching circuit.

28. The processor of claim 27, wherein the control logic is adapted to set the value on the output of the control logic in response to the relative values of a value at the first input of the control logic and a value at the second input of the control logic.

29. The processor of claim 26, wherein:

a) the rename circuit additionally comprises a second counter and a vector length register holding a value and the second counter is adapted to count in increments determined by the value in the vector length register;

b) the arithmetic circuit has a third input coupled to the second counter; and

c) the arithmetic circuit is configured to provide at the renamed output a value representing the value at the first input offset by an amount proportional to the value at the second input and offset by the value at the third input.

30. The processor of claim 21, wherein the processor comprises at least a first pipeline stage and a second pipeline stage and the decode circuit is within the first pipeline stage and the rename circuit is within the second pipeline stage.