Layered chip package and method of manufacturing same
First Claim
1. A method of manufacturing a layered chip package, the layered chip package comprising:
- a main body having a top surface, a bottom surface and four side surfaces; and
wiring disposed on at least one of the side surfaces of the main body, wherein;
the main body includes a plurality of layer portions stacked;
each of the plurality of layer portions includes;
a semiconductor chip having a top surface, a bottom surface and four side surfaces;
an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;
the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;
each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and
the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions,the method comprising the steps of;
fabricating a plurality of substructures that respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and
completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body,wherein the step of fabricating the plurality of substructures includes, as a series of steps for fabricating each substructure,the step of fabricating a pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;
the step of forming at least one groove in the pre-substructure wafer, the at least one groove opening at the first surface of the pre-substructure wafer and extending to be adjacent to at least one of the pre-semiconductor-chip portions;
the step of forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and
the step of forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer,wherein, in the step of completing the layered chip package, the insulating layer is cut to form a cut surface along a direction in which the at least one groove extends, whereby part of the at least one end face of the insulating portion is formed by the cut surface of the insulating layer and the end faces of the plurality of electrodes are exposed.
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Accused Products
Abstract
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.
21 Citations
18 Claims
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1. A method of manufacturing a layered chip package, the layered chip package comprising:
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a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes;
a semiconductor chip having a top surface, a bottom surface and four side surfaces;
an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, the method comprising the steps of; fabricating a plurality of substructures that respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body, wherein the step of fabricating the plurality of substructures includes, as a series of steps for fabricating each substructure, the step of fabricating a pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device; the step of forming at least one groove in the pre-substructure wafer, the at least one groove opening at the first surface of the pre-substructure wafer and extending to be adjacent to at least one of the pre-semiconductor-chip portions; the step of forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and the step of forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer, wherein, in the step of completing the layered chip package, the insulating layer is cut to form a cut surface along a direction in which the at least one groove extends, whereby part of the at least one end face of the insulating portion is formed by the cut surface of the insulating layer and the end faces of the plurality of electrodes are exposed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A layered chip package comprising:
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a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; and wiring disposed on the first side surface of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; the second, third and fourth side surfaces of the semiconductor chip are respectively located at the second, third and fourth side surfaces of the main body; the first side surface of the semiconductor chip faces toward the first side surface of the main body; each of the plurality of layer portions further includes;
an insulating portion covering the first side surface of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;the insulating portion has an end face located at the first side surface of the main body; each of the plurality of electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions.
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17. A layered chip package comprising:
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a main body having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; first wiring disposed on the first side surface of the main body; and second wiring disposed on the second side surface of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes a semiconductor chip having a top surface, a bottom surface, first and second side surfaces facing toward opposite directions, and third and fourth side surfaces facing toward opposite directions; the third and fourth side surfaces of the semiconductor chip are respectively located at the third and fourth side surfaces of the main body; the first and second side surfaces of the semiconductor chip respectively face toward the first and second side surfaces of the main body; each of the plurality of layer portions further includes;
an insulating portion covering the first and second side surfaces of the semiconductor chip; and
a plurality of first electrodes and a plurality of second electrodes connected to the semiconductor chip;the insulating portion has a first end face located at the first side surface of the main body, and a second end face located at the second side surface of the main body; each of the plurality of first electrodes has an end face located at the first side surface of the main body and surrounded by the insulating portion; each of the plurality of second electrodes has an end face located at the second side surface of the main body and surrounded by the insulating portion; the first wiring is connected to the end faces of the plurality of first electrodes of the plurality of layer portions; and the second wiring is connected to the end faces of the plurality of second electrodes of the plurality of layer portions.
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18. A layered chip package substructure for use for manufacturing a layered chip package, the layered chip package comprising:
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a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body, wherein; the main body includes a plurality of layer portions stacked; each of the plurality of layer portions includes;
a semiconductor chip having a top surface, a bottom surface and four side surfaces;
an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and
a plurality of electrodes connected to the semiconductor chip;the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, the layered chip package substructure corresponding to one of the plurality of layer portions of the layered chip package, including a plurality of its corresponding layer portions, and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions, the layered chip package substructure comprising a substructure main body fabricated by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the substructure main body including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device, wherein; the substructure main body has a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer, and has at least one groove that opens at the first surface of the substructure main body and that extends to be adjacent to at least one of the pre-semiconductor-chip portions; and the at least one groove has a bottom that does not reach the second surface of the substructure main body, the layered chip package substructure further comprising; an insulating layer that fills the at least one groove and that will later become part of the insulating portion; and the plurality of electrodes each having a portion lying on the insulating layer.
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Specification