APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM FOR TESTING A PANEL OF INTERFEROMETRIC MODULATORS

• US 20090319218A1
• Filed: 06/24/2008
• Published: 12/24/2009
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Yu, Tao, Chen, Lei, Nachman, Ramez
• Granted Patent: US 8,027,800 B2
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: B81C 99/0045 End test of the packaged device
• CPC Class Codes: G01R 31/302 Contactless testing G01R31/66 takes precedence
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

In some embodiments, each interferometric modulator has a stiction threshold voltage. If a voltage above the stiction threshold voltage is applied to the interferometric modulator, the interferometric modulator enters a stiction state permanently, i.e., becomes “stuck,” and the interferometric modulator becomes inoperable. Disclosed are apparatuses, methods and computer-readable media for testing a panel of interferometric modulators. A ramped voltage waveform is applied to a plurality of interferometric modulators of the panel. In response to applying the ramped voltage, the stiction threshold voltage is identified. At or above this voltage, the number of stuck interferometric modulators in the panel reaches or exceeds a first threshold number, for example, 50% of the total number of the interferometric modulators constituting the panel. The embodiments can be used to establish stiction benchmark for panel manufacturing processes, to collect data for generating statistical distribution, etc.

Claims

1. A method of testing a panel comprising a plurality of interferometric modulators, the method comprising:

applying a ramped voltage waveform to the plurality of interferometric modulators of the panel; and

in response to applying the ramped voltage, identifying a first voltage of the ramped voltage waveform at which a first threshold number of the plurality of interferometric modulators of the panel enter a stiction state, wherein with respect to an interferometric modulator that enters the stiction state, a first portion of the interferometric modulator adheres to a second portion of the interferometric modulator.

2. The method of claim 1, wherein the identifying the first voltage comprises optically detecting a number of the interferometric modulators that enter the stiction state.

3. The method of claim 1, wherein the identifying the first voltage comprises calculating a number of the interferometric modulators that enter the stiction state by measuring a capacitance of the panel.

4. The method of claim 1, wherein the identifying the first voltage comprises identifying a number of the interferometric modulators that enter the stiction state by taking an image of the panel and analyzing the image.

5. The method of claim 1, additionally comprising comparing, in an electronic device, the identified first voltage and an actuation threshold voltage of the panel.

6. The method of claim 5, additionally comprising comparing a first parameter that is based at least in part upon the identified first voltage and one of the actuation threshold voltage and a voltage bias of the panel with a second parameter that is based at least in part upon an identified first voltage and one of an actuation threshold voltage and a voltage bias of another panel.

7. The method of claim 1, additionally comprising:

identifying a second voltage at which a second threshold number of the plurality of interferometric modulators of the panel do not enter the stiction state; and

terminating applying the voltage subsequent to the ramped voltage reaching the second voltage.

8. The method of claim 1, wherein the ramped voltage waveform is applied starting at an offset voltage of the panel.

9. The method of claim 8, wherein the ramped voltage waveform is charge-balanced.

10. The method of claim 9, wherein the ramped voltage waveform comprises a first portion at which the plurality of interferometric modulators of the panel are in a released state, a second portion at which the plurality of interferometric modulators of the panel are in an actuated state, and a third portion at which the predetermined proportion of the plurality of interferometric modulators of the panel are in a stiction state.

11. The method of claim 1, wherein the panel comprises one of a plurality of panels in a plate.

12. An apparatus for testing a panel comprising a plurality of interferometric modulators, comprising:

a voltage source configured to apply a ramped voltage waveform to the plurality of interferometric modulators of the panel;

a detector configured to detect whether a number of the plurality of interferometric modulators of the panel are in a stiction state, wherein with respect to an interferometric modulator that is in the stiction state, a first portion of the interferometric modulator adheres to a second portion of the interferometric modulator; and

a processor configured to communicate with the voltage source and the detector and identify a first voltage at which a first threshold number of the plurality of interferometric modulators of the panel enter the stiction state.

13. The apparatus of claim 12, wherein the detector is configured to optically detect the number of the interferometric modulators in the stiction state.

14. The apparatus of claim 12, wherein the detector is configured to calculate the number of the interferometric modulators in the stiction state by measuring a capacitance of the panel.

15. The apparatus of claim 12, wherein the detector comprises a camera configured to identify a number of the interferometric modulators that enter the stiction state by taking an image of the panel and analyzing the image.

16. The apparatus of claim 12, wherein the processor is additionally configured to compare the identified first voltage and an actuation threshold voltage of the panel.

17. The apparatus of claim 16, wherein the processor is additionally configured to compare a first parameter that is based at least in part upon the identified first voltage and one of the actuation threshold voltage and a voltage bias of the panel with a second parameter that is based at least in part upon an identified first voltage and one of an actuation threshold voltage and a voltage bias of another panel.

18. The apparatus of claim 12, wherein the processor is additionally configured to identify a second voltage at which a second threshold number of the plurality of interferometric modulators of the panel do not enter the stiction state;

and

wherein the voltage source is additionally configured to terminate applying the voltage subsequent to the ramped voltage reaching the second voltage.

19. The apparatus of claim 12, wherein the voltage source applies the ramped voltage waveform starting at an offset voltage of the panel.

20. The apparatus of claim 19, wherein the ramped voltage waveform is charge-balanced.

21. The apparatus of claim 20, wherein the ramped voltage waveform comprises a first portion at which the plurality of interferometric modulators of the panel are in a released state, a second portion at which the plurality of interferometric modulators of the panel are in an actuated state, and a third portion at which the predetermined proportion of the plurality of interferometric modulators of the panel are in a stiction state.

22. The apparatus of claim 12, wherein the panel is one of a plurality of panels that constitute a plate.

23. An apparatus for testing a panel comprising a plurality of interferometric modulators, comprising:

means for applying a ramped voltage waveform to the plurality of interferometric modulators of the panel; and

means for, in response to applying the ramped voltage, identifying a first voltage at which a first threshold number of the plurality of interferometric modulators of the panel enter a stiction state, wherein with respect to an interferometric modulator that enters the stiction state, a first portion of the interferometric modulator adheres to a second portion of the interferometric modulator.

24. The apparatus of claim 23, wherein the means for identifying the first voltage comprises means for optically detecting a number of the interferometric modulators that enter the stiction state.

25. The apparatus of claim 23, wherein the means for identifying the first voltage comprises means for identifying a number of the interferometric modulators that enter the stiction state by taking an image of the panel and analyzing the image.

26. A computer-readable medium having stored thereon instructions, comprising:

instructions that, when executed by a computer, cause the computer to apply a ramped voltage waveform to a plurality of interferometric modulators of a panel; and

instructions that, when executed by the computer, cause the computer to in response to applying the ramped voltage, identify a first voltage at which a first threshold number of the plurality of interferometric modulators of the panel enter a stiction state, wherein with respect to an interferometric modulator that enters the stiction state, a first portion of the interferometric modulator adheres to a second portion of the interferometric modulator.

27. The computer-readable medium of claim 26, further comprising instructions that cause the computer to optically detect a number of the interferometric modulators that enter the stiction state.

28. The computer-readable medium of claim 26, further comprising instructions that cause the computer to calculate a number of the interferometric modulators that enter the stiction state by measuring a capacitance of the panel.

29. The computer-readable medium of claim 26, further comprising instructions that cause the computer to identify a number of the interferometric modulators that enter the stiction state by taking an image of the panel and analyzing the image.

30. The computer-readable medium of claim 26, further comprising instructions that cause the computer to compare the identified first voltage and an actuation threshold voltage of the panel.

31. The computer-readable medium of claim 30, further comprising instructions that cause the computer to compare a first parameter that is based at least in part upon the identified first voltage and one of the actuation threshold voltage and a voltage bias of the panel with a second parameter that is based at least in part upon an identified first voltage and one of an actuation threshold voltage and a voltage bias of another panel.

32. The computer-readable medium of claim 26, further comprising instructions that cause the computer to:

identify a second voltage at which a second threshold number of the plurality of interferometric modulators of the panel do not enter the stiction state; and

terminate applying the voltage subsequent to the ramped voltage reaching the second voltage.