Baseband Controller in a Micronetwork

• US 20090325490A1
• Filed: 08/31/2009
• Published: 12/31/2009
• Est. Priority Date: 11/08/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lin, John
• Granted Patent: US 7,974,578 B2
• Time in Patent Office: Days
• US Class Current: 455/41.2
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks

Abstract

A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time micronetwork functionality for an upper limit of slave devices. The microsequencer includes a correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with an arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating micronetwork timing functionality, and at registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

Claims

1. A baseband controller system to concurrently accommodate a plurality of slaves on a real-time basis in a micronetwork comprises:

transceiver circuitry to form a radio frequency link with the plurality of slaves;

a microsequencer coupled to the transceiver circuitry, wherein the microsequencer includes;

a correlator/accumulator for processing in a given computation

a plurality of clocks;

timer logic coupled to a plurality of timers sufficient to accommodate an upper limit of timer requests, the plurality of timers driven by the plurality of clocks to facilitate a micronetwork timing functionality; and

data storage logic coupled to a plurality of registers, the data storage logic operable to store and retrieve data to and from a register of the plurality of registers.

2. The baseband controller system of claim 1 wherein each of the plurality of registers are of a different size.

3. The baseband controller system of claim 1 wherein each of the plurality of registers include a 64-bit register, a 48-bit register, a 32-bit register and a 16-bit register.

4. The baseband controller system of claim 3 wherein the data storage logic determine which register to store the data based upon a size of the data.

5. The baseband controller system of claim 1 wherein the plurality of clocks include at least four clocks.

6. The baseband controller system of claim 1 wherein the plurality of timers include eight timers.

7. A microsequencer for a real-time micronetwork baseband controller, comprises:

timer circuitry to accommodate an upper limit of timer requests, the plurality of timers driven by the plurality of clocks to facilitate a micronetwork timing functionality;

temporary data storage circuitry; and

a plurality of external micronetwork and native clocks coupled to drive the timer circuitry based upon a micronetwork timing functionality according to a micronetwork specification.

8. The microsequencer of claim 7 wherein the plurality of external micronetwork and native clocks include an external real-time clock, wherein an external master clock drives the external real-time clock.

9. The microsequencer of claim 7 wherein the temporary data storage circuitry includes a 64-bit register, a 48-bit register, a 32-bit register and a 16-bit register.

10. The microsequencer of claim 7 wherein the temporary data storage circuitry comprises:

a plurality of registers, wherein each register is of a different size;

a data storage logic module coupled to the plurality of registers, wherein the data storage logic module determines which register to use based upon the size of data that is to be temporarily stored.

11. The microsequencer of claim 7 wherein the timers include at least four timers.

12. The microsequencer of claim 7 wherein the timers include at least eight timers.

13. The microsequencer of claim 7 further including timer control logic circuitry for controlling the operation of the at least eight timers.