Memory System with Calibrated Data Communication

  • US 20090327789A1
  • Filed: 04/27/2009
  • Published: 12/31/2009
  • Est. Priority Date: 10/19/1999
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a memory device including;

    a first receiver to receive a calibration sequence, the receiver to provide receiver data based on a phase difference between the calibration sequence and a reference clock signal, anda first transmitter to output the receiver data; and

    a controller device coupled to the memory device, the controller device including;

    a second transmitter to output the calibration sequence to the memory device,a second receiver to receive the receiver data, andwherein the controller device is configured to determine a timing offset to apply to write data output by the controller device, wherein the timing offset is determined based on a threshold number of bit errors detected in the receiver data.

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