Memory System with Calibrated Data Communication

• US 20090327789A1
• Filed: 04/27/2009
• Published: 12/31/2009
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Kim, Jun, Stark, Donald C., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Yu, Leung, Lau, Benedict Chung-Kwong, Vu, Roxanne, Zerbe, Jared LeVan, Ho, Tsyr-Chyang
• Granted Patent: US 8,170,067 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Claims

1. A system comprising:

a memory device including;

a first receiver to receive a calibration sequence, the receiver to provide receiver data based on a phase difference between the calibration sequence and a reference clock signal, and

a first transmitter to output the receiver data; and

a controller device coupled to the memory device, the controller device including;

a second transmitter to output the calibration sequence to the memory device,

a second receiver to receive the receiver data, and

wherein the controller device is configured to determine a timing offset to apply to write data output by the controller device, wherein the timing offset is determined based on a threshold number of bit errors detected in the receiver data.

2. The system of claim 1, further comprising:

a control line coupled to the controller device and the memory device; and

a termination resistor coupled to the control line such that a control signal, transmitted by the controller device onto the control line, propagates past the memory device before reaching the termination resistor.

3. The system of claim 1, further comprising:

a locked loop circuit on the controller device, the locked loop circuit to generate a transmit clock signal, the second transmitter to output the calibration sequence in response to the transmit clock signal; and

a signal line to carry the reference clock signal from the controller device to the memory device.

4. The system of claim 1, wherein the timing offset is determined during a calibration phase of system operation.

5. The system of claim 1, wherein the timing offset is determined periodically during system operation.

6. The system of claim 1, wherein the receiver data is stored in the memory device before being output by the first transmitter.

7. The system of claim 1, wherein the calibration sequence includes a predetermined number of signaling transitions.

8. The system of claim 1, wherein the controller device is configured to determine the timing offset by (i) outputting the calibration sequence including a single data transition, (ii) reading back the calibration sequence, (iii) determining where a transition occurs in the read calibration sequence, (iv) adjusting an initial timing offset value, and (v) repeating steps (i) to (iv) until the timing offset dithers back and forth between two offset values.

9. A method of operation in a memory system that includes a controller device coupled to a memory device, the method comprising:

transmitting a calibration sequence from the controller device to the memory device;

generating receiver data at the memory device based on a phase difference between the received calibration sequence and a reference clock signal;

transmitting the receiver data from the memory device to the controller device; and

generating, at the controller device, a value representative of a timing offset to apply to data output by a transmitter of the controller device, wherein the timing offset is determined based on a threshold number of bit errors in the receiver data.

10. The method of claim 9, wherein generating the value is performed during a calibration phase of system operation.

11. The method of claim 9, wherein generating the value is performed periodically during system operation.

12. A system comprising:

a first integrated circuit device including;

a first receiver to sample a calibration sequence, the receiver to provide receiver data based on a phase difference between the calibration sequence and a reference clock signal, and

a first transmitter to output the receiver data; and

a second integrated circuit device coupled to the first integrated circuit device, the second integrated circuit device including;

a second transmitter to output the calibration sequence to the first integrated circuit device,

a second receiver to receive the receiver data, and

wherein the second integrated circuit device is configured to determine a timing offset to apply to write data output by the second integrated circuit device, wherein the timing offset is determined based on a threshold number of bit errors in the receiver data.

13. The system of claim 12, wherein the first integrated circuit device is a transceiver and the second integrated circuit device is a controller.

14. The system of claim 12, wherein the first integrated circuit device is a controller and the second integrated circuit device is a transceiver.

15. The system of claim 12, wherein the first integrated circuit device is a memory device and the second integrated circuit device is a controller that accesses data stored in the memory device.

16. The system of claim 12, further comprising a locked loop circuit on the second integrated circuit device, the locked loop circuit to generate a receive clock signal, wherein the first receiver samples the calibration sequence in response to the receive clock signal.

17. The system of claim 16, further comprising a signal line to carry the reference clock signal from the second integrated circuit device to the first integrated circuit device, and wherein the receive clock signal is generated based on the reference clock signal.

18. The system of claim 12, wherein the timing offset is determined using a calibration phase of system operation.

19. The system of claim 12, wherein the timing offset is calibrated periodically during system operation.

20. The system of claim 12, wherein the second integrated circuit device is configured to determine the timing offset by (i) outputting the calibration sequence including a single data transition, (ii) reading back the calibration sequence, (iii) determining where a transition occurs in the read calibration sequence, (iv) adjusting an initial timing offset value, and (v) repeating steps (i) to (iv) until the timing offset dithers back and forth between two offset values.