Channel layers and semiconductor devices including the same

• US 20100006834A1
• Filed: 07/14/2009
• Published: 01/14/2010
• Est. Priority Date: 07/14/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Kim, Sang-wook, Song, I-hun, Park, Jae-chul, Kim, Chang-jung
• Granted Patent: US 8,232,551 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

Claims

1. A semiconductor device, comprising:

a multi-layer channel including at least a first layer and a second layer which have different carrier mobilities and formed of different oxide materials;

a source on the multi-layer channel layer;

a drain on the multi-layer channel layer, separated from the source; and

a gate on the multi-layer channel layer.

2. The semiconductor device of claim 1, wherein the first layer is closer to the gate than the second layer and the first layer has a higher carrier mobility than the second layer.

3. The semiconductor device of claim 1, wherein the first layer predominantly determines a mobility of the semiconductor device.

4. The semiconductor device of claim 1, wherein a threshold voltage of the semiconductor device is predominantly determined by one of the first and second layers.

5. The semiconductor device of claim 1, wherein the first layer is closer to the gate than the second layer, and

the first layer includes at least one oxide selected from the group consisting of indium zinc oxide (IZO), indium tin oxide (ITO), aluminum zinc oxide (AZO) and gallium zinc oxide (GZO).

6. The semiconductor device of claim 1, wherein the second layer includes a ZnO-based material.

7. The semiconductor device of claim 1, wherein the first layer has a thickness of about 10 Å

to about 500 Å

.

8. The semiconductor device of claim 7, wherein the first layer has a thickness of about 30 Å

to about 200 Å

.

9. The semiconductor device of claim 1, wherein the semiconductor device is one of a top gate or a bottom gate thin film transistor (TFT).

10. A semiconductor device comprising:

a multi-layer channel including at least a lower layer and an upper layer which have different carrier densities and formed of different oxide materials;

a source on the multi-layer channel layer;

a drain on the multi-layer channel layer, separated from the source; and

a gate on the multi-layer channel layer.

11. The semiconductor device of claim 10, wherein the first layer is closer to the gate than the second layer and the first layer has a higher carrier density than the second layer.

12. The semiconductor device of claim 10, wherein the first layer and the second layer have different carrier mobilities.

13. The semiconductor device of claim 12, wherein the first layer is closer to the gate than the second layer,

the first layer has a higher carrier mobility than the second layer, and

the first layer predominantly determines a mobility of the semiconductor device.

14. The semiconductor device of claim 10, wherein one of the lower layer and the upper layer, which is closer to the gate, determines a mobility of the semiconductor device.

15. The semiconductor device of claim 10, wherein a threshold voltage of the semiconductor device is predominantly determined by at least one of the first layer and the second layer.

16. The semiconductor device of claim 10, wherein the first layer includes at least one oxide selected from the group consisting of indium zinc oxide (IZO), indium tin oxide (ITO), aluminum zinc oxide (AZO) and gallium zinc oxide (GZO).

17. The semiconductor device of claim 10, wherein the second layer includes a ZnO-based material.

18. The semiconductor device of claim 10, wherein the first layer has a thickness of about 10 Å

to about 500 Å

.

19. The semiconductor device of claim 18, wherein the first layer has a thickness of about 30 Å

to about 200 Å

.

20. The semiconductor device of claim 10, wherein the semiconductor device is one of a top gate or a bottom gate thin film transistor (TFT).