Structure and Method for Forming Trench Gate Transistors with Low Gate Resistance

• US 20100013009A1
• Filed: 12/12/2008
• Published: 01/21/2010
• Est. Priority Date: 12/14/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Pan, James
• Application Number:
  US12/333,707
• Publication Number:
  US 20100013009A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench.

Claims

1. A field effect transistor (FET), comprising:

body regions of a first conductivity type over a semiconductor region of a second conductivity type, the body regions forming p-n junctions with the semiconductor region;

trenches extending through the body region and terminating within the semiconductor region;

source regions of the second conductivity type over the body regions adjacent the trenches, the source regions forming p-n junctions with the body regions;

a gate dielectric layer lining sidewalls of each trench;

a metal liner lining the gate dielectric layer in each trench; and

a gate electrode comprising metallic material disposed in each trench.

2. The FET of claim 1 further comprising:

contact openings extending into the body regions between adjacent trenches;

a heavy body region of the first conductivity type extending in each body region along the bottom of each contact opening; and

an interconnect layer filling each contact opening and being in direct contact with source regions along sidewalls of the contact openings.

3. The FET of claim 2, wherein top surfaces of the source regions are fully covered by a dielectric cap material such that the interconnect layer makes direct contact with the source regions only along sidewalls of the contact openings.

4. The FET of claim 1, wherein the gate dielectric layer comprises high-k dielectric.

5. The FET of claim 1, wherein each trench further includes a shield electrode disposed below the gate electrode, the gate and shield electrodes being insulated from one another by an inter-electrode dielectric layer.

6. The FET of claim 1, wherein each trench further includes a thick bottom dielectric extending along the bottom of the trench below the gate electrode.

7. A method of forming a field effect transistor (FET), comprising:

forming body regions of a first conductivity type in a semiconductor region of a second conductivity type, the body regions forming p-n junctions with the semiconductor region;

forming trenches extending into the semiconductor region;

forming source regions of the second conductivity type over the body regions adjacent the trenches, the source regions forming p-n junctions with the body regions;

forming a gate dielectric layer lining sidewalls of each trench;

forming a metal liner lining the gate dielectric layer in each trench; and

forming a metallic gate electrode in each trench, the metallic gate electrode comprising metallic material.

8. The method of claim 7 further comprising:

forming contact openings extending into the body regions between adjacent trenches;

forming a heavy body region of the first conductivity type extending in each body region along the bottom of each contact opening; and

forming an interconnect layer filling each contact opening and being in direct contact with source regions along sidewalls of the contact openings.

9. The method of claim 8 further comprising:

forming a dielectric cap material fully covering top surfaces of the source regions such that the interconnect layer makes direct contact with the source regions only along sidewalls of the contact openings.

10. The method of claim 7, wherein the gate dielectric layer comprises high-k dielectric.

11. The method of claim 7 further comprising:

before forming the gate electrodes;

forming a shield dielectric layer lining lower sidewalls and bottom of each trench;

forming a shield electrode in a lower portion of each trench; and

forming an inter-electrode dielectric layer in each trench over the shield electrode.

12. The method of claim 7 further comprising:

before forming the metallic gate electrode;

forming a polysilicon gate material in each trench; and

removing the polysilicon gate material from each trench.

13. The method of claim 7, wherein the metallic material comprises tungsten.

14. The method of claim 7, wherein the metallic gate electrode is formed after forming the body region.