ESD Protection Structures on SOI Substrates

• US 20100013016A1
• Filed: 07/18/2008
• Published: 01/21/2010
• Est. Priority Date: 07/18/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Shih, Jiaw-Ren
• Granted Patent: US 7,994,577 B2
• Time in Patent Office: Days
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Claims

1. An electrostatic discharge (ESD) protection circuit comprising:

a buried oxide layer;

a semiconductor layer on the buried oxide layer;

a first MOS device comprising;

a first gate over the semiconductor layer;

a first well region having a portion underlying the first gate; and

a first source region and a first drain region in the semiconductor layer and adjoining the first well region; and

a second MOS device comprising;

a second gate over the semiconductor layer;

a second well region having a portion underlying the first gate, wherein the second well region is connected to a discharging node selected from the group consisting essentially of ground and VDD, and wherein the first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node; and

a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

2. The ESD protection circuit of claim 1 further comprising a heavily doped well region in the semiconductor layer, wherein the heavily doped well region is of a same conductivity type as the first and the second well regions, and wherein the heavily doped well region adjoins the first and the second well regions.

3. The ESD protection circuit of claim 2:

wherein the first well region comprises;

a first end portion adjacent a first end of the first gate; and

a second end portion adjacent a second end of the first gate; and

wherein the second well region comprises;

a third end portion adjacent a first end of the second gate, wherein the second and the third end portions adjoin the heavily doped well region; and

a fourth end portion adjacent a second end of the second gate, wherein the second end portion is directly connected to the discharging node.

4. The ESD protection circuit of claim 1, wherein the first gate is connected to the discharging node, and the second gate is connected to a signal node.

5. The ESD protection circuit of claim 1 further comprising:

a plurality of ESD MOS devices, wherein each of the plurality of ESD MOS devices comprises a third source region connected to the first source region, a third drain region connected to the first drain region, and a third well region connected to the first well region; and

a plurality of input/output (IO) MOS devices, wherein each of the plurality of IO MOS devices comprises a fourth source region connected to the second source region, a fourth drain region connected to the second drain region, and a fourth well region connected to the second well region.

6. The ESD protection circuit of claim 1, wherein the first and the second well regions, the first and the second source regions, and the first and the second drain regions are in physical contact with the buried oxide layer.

7. The ESD protection circuit of claim 1, wherein the first and the second source regions are directly connected to the discharging node.

8. The ESD protection circuit of claim 1, wherein the first and the second drain regions are connected to an input/output pad.

9. The ESD protection circuit of claim 1, wherein the discharging node is Vdd, and wherein the first and the second well regions are n-well regions.

10. The ESD protection circuit of claim 1, wherein the discharging node is the ground, and wherein the first and the second well regions are p-well regions.

11. An electrostatic discharge (ESD) protection circuit comprising:

a buried oxide layer;

a semiconductor layer on the buried oxide layer;

a first MOS device comprising;

a first gate over the semiconductor layer;

a first well region in the semiconductor layer and having a portion underlying the first gate, wherein the first well region comprises a first end portion adjacent a first end of the first gate, and a second end portion adjacent a second end of the first gate, and wherein the first well region is not directly connected to any ground; and

a first source region and a first drain region in the semiconductor layer;

a metal line interconnecting the first and the second end portions of the first well region; and

a second MOS device comprising;

a second gate over the semiconductor layer; and

a second well region in the semiconductor layer and having a portion underlying the second gate, wherein the second well region comprises a third end portion connected to the second end portion of the first gate, and a fourth end portion directly connected to a ground.

12. The ESD protection circuit of claim 11 further comprising a heavily doped well region adjoining, and has a same conductivity type as, the third end portion of the second well region and the second end portion of the first well region.

13. The ESD protection circuit of claim 11 further comprising:

an additional heavily doped region adjoining the fourth end portion of the second well region;

a contact plug connected to the additional heavily doped region; and

an additional metal line overlying and electrically connected to the contact plug, wherein the additional metal line is directly connected to the ground.

14. The ESD protection circuit of claim 11, wherein the first and the second well regions, the first and the second source regions, and the first and the second drain regions contact the buried oxide layer.

15. The ESD protection circuit of claim 11, wherein the first MOS device is an ESD device, and wherein the second MOS device is an input/output device.

16. An electrostatic discharge (ESD) protection circuit comprising:

a buried oxide layer;

a semiconductor layer on the buried oxide layer;

a first P+ region in the semiconductor layer;

a first contact plug over and connected to the first P+ region, wherein the first contact plug is directly connected to a ground;

a first p-well region in the semiconductor layer and adjoining the first P+ region;

a first gate over the first p-well region;

a second P+ region in the semiconductor layer and adjoining the first p-well region, wherein the second P+ region is on an opposite side of the first p-well region than the first P+ region;

a second contact plug over and connected to the second P+ region, wherein the second contact plug is not directly connected to the ground;

a second p-well region in the semiconductor layer and adjoining the second P+ region, wherein the first and the second p-well regions are physically separated from each other; and

a second gate over the second p-well region.

17. The ESD protection circuit of claim 16 further comprising:

a third P+ region in the semiconductor layer and adjoining the second p-well region, wherein the third P+ region is on an opposite side of the second p-well region than the second P+ region;

a third contact plug over and connected to the third P+ region; and

a metal line over and connecting the second and the third contact plugs, wherein the metal line is not directly connected to the ground.

18. The ESD protection circuit of claim 16, wherein the first gate is disconnected from the ground, and wherein the second gate is connected to the ground.

19. The ESD protection circuit of claim 18 further comprising:

a first source region in the semiconductor layer and adjoining the first p-well region; and

a second source region in the semiconductor layer and adjoining the second p-well region, wherein the first and the second source regions are directly connected to the ground.

20. The ESD protection circuit of claim 18 further comprising:

a first drain region in the semiconductor layer and adjoining the first p-well region; and

a second drain region in the semiconductor layer and adjoining the second p-well region, wherein the first and the second drain regions are connected to an external pad.