VOID-FREE IMPLANTABLE HERMETICALLY SEALED STRUCTURES

• US 20100016928A1
• Filed: 04/12/2007
• Published: 01/21/2010
• Est. Priority Date: 04/12/2006
• Status: Abandoned Application

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Islam, Mohammed Z., Zdeblick, Mark J., Costello, Benedict, Thompson, Todd, Jensen, Marc, Frank, Jeremy
• Application Number:
  US12/296,654
• Publication Number:
  US 20100016928A1
• Time in Patent Office: Days
• US Class Current: 607/72
• CPC Class Codes: A61N 1/05 for implantation or insertion into the body, e.g. heart electrode A61N1/06 takes precedence
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/63 Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01044 Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01076 Osmium [Os]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

An implantable integrated circuit structure comprising a conformal thin-film sealing layer for hermetically sealing circuitry layers is provided. Also disclosed are electrode structures, leads that include the same, implantable pulse generators that include the leads, as well as systems and kits having components thereof, other implantable devices utilizing the structures, and methods of making and using the subject structures.

Claims

1. An implantable hermetically sealed structure comprising a conformal sealing layer over at least a portion of the outer surface of said structure to provide an implantable hermetically sealed structure.

2. The structure according to claim 1, wherein said conformal sealing layer covers all of the outer surface of said structure.

3. The structure according to claim 1, wherein said conformal sealing layer covers only a portion of the outer surface of said structure.

4. The structure according to claim 1, wherein said structure is an integrated circuit.

5. The integrated circuit according to claim 4, wherein said circuit comprises:

a substrate;

a circuitry layer comprising an integrated circuit, wherein said circuitry layer is on and/or within a top surface of said substrate; and

a sealing layer on a top surface of said circuitry layer that hermetically seals said circuitry layer to provide an implantable hermetically sealed integrated circuit device.

6. The implantable hermetically sealed integrated circuit device of claim 5, wherein said sealing layer comprises an electrical via that provides electrical communication between said hermetically sealed circuitry layer and a location external to said hermetically sealed circuitry layer.

7. The implantable hermetically sealed integrated circuit device of claim 6, wherein said via comprises corrosion-resistant conductor element.

8. The implantable hermetically sealed integrated circuit device of claim 5, wherein said circuitry layer comprises a beveled edge.

9. The implantable hermetically sealed structure according to claim 1, wherein said structure is an implantable pulse generator.

14. An implantable medical device comprising a hermetically sealed integrated circuit device according to claim 5.

15. The implantable medical device according to claim 14, wherein said implantable medical device is lead of an implantable pulse generator.

16. An electrode assembly comprising an implantable hermetically sealed integrated circuit according to claim 5.

17. The electrode assembly according to claim 16, wherein said electrode assembly is a segmented electrode comprising two or more electrodes.

18. The electrode assembly according to claim 17, wherein said segmented electrode comprises four electrodes.

19. An elongated flexible structure comprising a proximal end and a distal end, and at least one electrode assembly according to claim 18.

20. The elongated flexible structure according to claim 19, wherein said structure is a vascular lead.

21. The elongated flexible structure according to claim 20, wherein said vascular lead comprises 2 or more electrode assemblies.

22. The elongated flexible structure according to claim 21, wherein said vascular lead is a multiplex lead having 3 or less wires.

23. An implantable pulse generator comprising:

(a) a housing comprising a power source and an electrical stimulus control element; and

(b) a vascular lead according to claim 20.

24. A method comprising:

implanting an implantable pulse generator according to claim 20 into a subject; and

using said implanted pulse generator.

10. A method of fabricating an implantable hermetically sealed integrated circuit, said method comprising:

providing a circuitry layer on a top surface of a substrate; and

producing a sealing layer on a top surface of said circuitry layer that hermetically seals said circuitry layer to provide said implantable hermetically sealed integrated circuit device.

11. The method according to claim 10, wherein said sealing layer is produced on said top surface of the substrate.

12. The method according to claim 11, wherein producing said sealing layer comprises depositing a sealing layer material on said top surface of said circuitry layer.

13. The method according to claim 12, wherein said sealing layer is deposited by a process selected from a group consisting of plasma vapor deposition, plasma enhanced chemical vapor deposition, sputtering, e-beam evaporation, plating, cathodic arc deposition and low-pressure chemical vapor deposition.