Method and Apparatus for N+1 Packet Level Mesh Protection

• US 20100017687A1
• Filed: 09/23/2009
• Published: 01/21/2010
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Langner, Paul
• Granted Patent: US 8,271,847 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.

Claims

1. An error correction decoding method, comprising:

receiving a plurality of error-free packets and one or more packets having an error; and

reconstructing said one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode said received packets.

2. The method of claim 1 wherein said block erasure decoder is a Bit Interleaved Parity (BIP-8) or byte-wise exclusive OR function.

3. The method of claim 1, further comprising the step of removing any padding at the end of said plurality of packets.

4. An error correction decoder, comprising:

a memory; and

at least one processor, coupled to the memory, operative to;

receive a plurality of error-free packets and one or more packets having an error; and

reconstruct said one or more packets having an error by applying a block erasure decoder to a said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode said received packets.

5. The error correction decoder of claim 4, wherein said block erasure decoder is a bytewise exlusive OR or BIP-8.

6. The error correction decoder of claim 4, further comprising the step of removing any padding at the end of said M packets.