VOLTAGE REGULATOR WITH RIPPLE COMPENSATION

• US 20100026251A1
• Filed: 07/29/2008
• Published: 02/04/2010
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Lam, Nelson S. H., Toffolon, Dino A.
• Granted Patent: US 8,405,371 B2
• Time in Patent Office: Days
• US Class Current: 323/273
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

Embodiments of the present invention provide a voltage regulator. The voltage regulator includes a driving mechanism coupled to an output node (VREG), wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node. In addition, the voltage regulator includes a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in the output node voltage when a load coupled to the output node requires a transient switching current that is faster than the loop response time of the driving mechanism. Furthermore, the boost circuit is biased using a self-tracking mechanism to provide accurate duration and level of the current to the output node in a transient switching event.

Claims

1. An apparatus for regulating voltage, comprising:

a driving mechanism coupled to an output node, wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node; and

a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in a voltage of the output node when a load coupled to the output node requires a transient switching current on the output node that must be provided faster than the loop response time of the driving mechanism.

2. The apparatus of claim 1, wherein the boost circuit comprises:

a compensation mechanism coupled to the output node; and

a detection mechanism coupled to the compensation mechanism;

wherein the detection mechanism monitors the load on the output node to determine when the load on the output node will require the transient switching current and signals the compensation mechanism to drive the additional current onto the output node.

3. The apparatus of claim 2, wherein the compensation mechanism comprises:

a current source; and

a switch coupled between the current source and the output node;

wherein the switch is coupled to the detection mechanism and wherein the switch is configured to remain open until the detection mechanism closes the switch; and

wherein when signaling the compensation mechanism, the detection mechanism is configured to close the switch, causing a current to be driven from the current source to the output node.

4. The apparatus of claim 3, wherein the switch comprises a first MOS transistor and the current source comprises a second MOS transistor;

wherein the detection mechanism is configured to hold the first MOS transistor in a cut-off operating region when the switch is open, and in a linear operating region when the switch is closed; and

wherein the second MOS transistor is coupled to a biasing circuit that biases the second MOS transistor so that the second MOS transistor provides current to the output node when the first MOS transistor is in the linear operating region.

5. The apparatus of claim 2, further comprising:

a circuit coupled to the output node, wherein the circuit is configured to use the output node as a power supply at the predetermined voltage, thereby placing a load on the output node.

6. The apparatus of claim 5, further comprising:

one or more monitoring signals;

wherein each monitoring signal is coupled between the detection mechanism and one or more separate internal nodes, clock signals, synchronization signals, or other locations in the circuit; and

wherein the detection mechanism is configured to use the monitoring signals to determine when the load on the output node will require the transient switching current.

7. The apparatus of claim 5, wherein the circuit coupled to the output node includes one or more:

high-definition media interface (HDMI);

10-gigabit Ethernet (XAUI) protocol;

serial advanced technology attachment (SATA) protocol;

peripheral component interface express (PCIe);

or

universal serial bus (USB) circuits.

8. The apparatus of claim 5, wherein the boost circuit is configured so that the duration of a current that is driven to the output node is proportional to the duration of transient switching events that occur in an output driver in the circuit.

9. The apparatus of claim 1, wherein the boost circuit is configured so that the amplitude of the current that is driven to the output node is proportional to the VREG node voltage and scales over process corners.

10. A method for regulating voltage, comprising:

providing current from a driving mechanism to an output node to sustain a predetermined voltage on the output node; and

driving an additional current from a boost circuit to the output node to reduce fluctuations in a voltage of the output node when a load coupled to the output node requires a transient switching current on the output node that must be provided faster than the loop response time of the driving mechanism.

11. The method of claim 10, wherein driving the additional current from the boost circuit involves:

using a detection mechanism in the boost circuit to monitor the load on the output node to determine when the load on the output node will require the transient switching current; and

signaling a compensation mechanism in the boost circuit to drive the additional current onto the output node when the load requires the transient switching current on the output node.

12. The method of claim 11, wherein the compensation mechanism comprises a current source and a switch coupled between the current source and the output node, wherein a control for the switch is coupled to the detection mechanism, wherein the method further comprises:

holding the switch open until a signal from the detection mechanism activates the control to close the switch; and

when signaling the compensation mechanism, activating the control using the detection mechanism to close the switch, causing a current to be driven from the current source to the output node.

13. The method of claim 12, wherein the switch comprises a first MOS transistor and the current source comprises a second MOS transistor, wherein a gate connection of the second MOS transistor is coupled to a biasing circuit, and wherein the method further comprises:

holding the first MOS transistor in a cut-off operating region when the switch is open, and in a linear operating region when the switch is closed; and

using the biasing circuit to bias the second MOS transistor so that the second MOS transistor provides current to the output node when the first MOS transistor is in the linear operating region.

14. The method of claim 10, wherein a circuit is coupled to the output node, wherein the circuit is configured to use the output node as a power supply at the predetermined voltage and one or more monitoring signals are coupled between the detection mechanism and one or more separate internal nodes, clock signals, synchronization signals, or other locations in the circuit, and wherein the method further comprises:

using the monitoring signals to determine when the load require the transient switching current on the output node.

15. The method of claim 14, wherein the circuit coupled to the output node includes one or more:

high-definition media interface (HDMI);

10-gigabit Ethernet (XAUI) protocol;

serial advanced technology attachment (SATA) protocol;

peripheral component interface express (PCIe);

or

universal serial bus (USB) circuits.

16. The method of claim 14, wherein the duration of the additional current that is driven to the output node is proportional to the duration of transient switching events that occur in an output driver in a circuit that is coupled to the output node.

17. The apparatus of claim 10, wherein the amplitude of the additional current that is driven to the output node is proportional to the VREG node voltage and scales over process corners.

18. An electronic device, comprising:

one or more circuits coupled to an output node, wherein the output node is configured to provide power for the circuit at a predetermined voltage;

a driving mechanism coupled to an output node, wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node; and

a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in a voltage of the output node when the circuits require a transient switching current on the output node that must be provided faster than the loop response time of the driving mechanism.

19. The electronic device of claim 18, wherein the boost circuit comprises:

a compensation mechanism coupled to the output node; and

a detection mechanism coupled to the compensation mechanism;

wherein the detection mechanism monitors the load on the output node to determine when the load on the output node will require the transient switching current and signals the compensation mechanism to drive the additional current onto the output node.

20. The electronic device of claim 19, wherein the compensation mechanism comprises:

a current source; and

a switch coupled between the current source and the output node;

wherein the switch is coupled to the detection mechanism and wherein the switch is configured to remain open until the detection mechanism closes the switch; and

wherein when signaling the compensation mechanism, the detection mechanism is configured to close the switch, causing a current to be driven from the current source to the output node.

21. The electronic device of claim 20, wherein the switch comprises a first MOS transistor and the current source comprises a second MOS transistor;

wherein the detection mechanism is configured to hold the first MOS transistor in a cut-off operating region when the switch is open, and in a linear operating region when the switch is closed; and

wherein the second MOS transistor is coupled to a biasing circuit that biases the second MOS transistor so that the second MOS transistor provides current to the output node when the first MOS transistor is in the linear operating region.

22. The electronic device of claim 18, further comprising:

one or more monitoring signals;

wherein each monitoring signal is coupled between the detection mechanism and one or more separate internal nodes, clock signals, synchronization signals, or other locations in the circuit; and

wherein the detection mechanism is configured to use the monitoring signals to determine when the load on the output node will require the transient switching current.

23. The electronic device of claim 18, wherein the circuit coupled to the output node includes one or more:

high-definition media interface (HDMI);

10-gigabit Ethernet (XAUI) protocol;

serial advanced technology attachment (SATA) protocol;

peripheral component interface express (PCIe);

or

universal serial bus (USB) circuits.

24. The electronic device of claim 18, wherein the boost circuit is configured so that the duration of a current that is driven to the output node is proportional to the duration of transient switching events that occur in an output driver in the circuit.

25. The electronic device of claim 18, wherein the boost circuit is configured so that the amplitude of the current that is driven to the output node is proportional to the VREG node voltage and scales over process corners.