METHOD AND SYSTEM FOR RECONFIGURABLE CHANNEL CODING

• US 20100027597A1
• Filed: 10/13/2009
• Published: 02/04/2010
• Est. Priority Date: 05/08/2001
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Scheuermann, W. James
• Granted Patent: US 7,809,050 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 65/75 Media network packet handling
• CPC Class Codes: H04L 65/756 adapting media to device capabilities

Abstract

Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

Claims

1. A reconfigurable system for providing channel coding in a wireless communication device comprising:

a plurality of computation elements for performing channel coding operations, wherein the plurality of computation elements comprises a data reordering element, a linear feedback shift register (LFSR) element, and a convolutional encoder element, and wherein the convolutional encoder comprises a coupled configuration of an input shift register, a delay register, a plurality of polynomial generators, and an output shift register; and

a controller for reconfigurably controlling the plurality of computation elements to achieve channel coding operations in accordance with a plurality of wireless communication standards,

wherein the channel coding operations are bit-oriented and wherein the memory and the plurality of computation elements are byte-oriented, and wherein the at least one of the plurality of computation elements is configured to map the bit-oriented operations to the byte-oriented memory and plurality of computation elements.

2. The reconfigurable system of claim 1 further comprising memory for storing programs, and wherein the stored programs comprise instructions for reconfiguring the plurality of computational elements for the channel coding operations.

3. The reconfigurable system of claim 1 wherein each of the plurality of computation elements comprises memory for storing programs, and wherein the stored programs comprise instructions for executing commands for the channel coding operations.

4. The reconfigurable system of claim 1 wherein each of the plurality of polynomial generators further comprises a configuration register, an AND logic means, and an exclusive-OR logic means.

5. The reconfigurable system of claim 1 wherein the plurality of computation elements further comprises a Viterbi decoder element.

6. The reconfigurable system of claim 5 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.

7. A method for providing channel coding in a wireless communication device comprising:

selecting one of a plurality of wireless communication standards; and

reconfigurably controlling a plurality of computation elements to achieve channel coding operations in accordance with the selected wireless communication standard, wherein the plurality of computation elements wherein the plurality of computation elements perform data reordering, perform the operations of a linear feedback shift register (LFSR), and convolutional encoding, and wherein convolutional encoding comprises performing operations of an input shift register, a delay register, a plurality of polynomial generators and an output shift register,

wherein the channel coding operations are bit-oriented and wherein the memory and the plurality of computation elements are byte-oriented, and wherein controlling comprises mapping the bit-oriented operations to the byte-oriented memory and plurality of computation elements.

8. The method of claim 7, further comprising selecting a mode of the selected one of the plurality of wireless communication standards.

9. The method of claim 7, wherein selecting one of the plurality of wireless communication standards comprises:

receiving a signal associated with one of the plurality of wireless communication standards; and

identifying the one of the plurality of wireless communication standards based on the coding of the signal.

10. The method of claim 7, wherein the plurality of computation elements comprises a data reordering element, a linear feedback shift register (LFSR) element, and a convolutional encoder, wherein the convolutional encoder further comprises a coupled configuration of an input shift register, a delay register, a plurality of polynomial generators, and an output shift register.

11. The method of claim 10, wherein the plurality of computation elements further comprises a Viterbi decoder element.

12. The method of claim 7, wherein mapping the bit-oriented operations to the byte-oriented memory and plurality of computation elements comprises processing eight information bits at a time and computing a LFSR state after eight consecutive shifts.

13. A reconfigurable system for providing channel coding in a wireless communication device comprising:

a plurality of computation elements for performing channel coding operations, wherein the plurality of computation elements comprises a data reordering element, a linear feedback shift register (LFSR) element, and a convolutional encoder, and wherein the convolutional encoder comprises a coupled configuration of an input shift register, a delay register, a plurality of polynomial generators, and an output shift register; and

a controller for reconfigurably controlling the plurality of computation elements to achieve channel coding operations in accordance with a plurality of wireless communication modes within a wireless communication standard,

wherein the channel coding operations are bit-oriented and wherein the memory and the plurality of computation elements are byte-oriented, and wherein the at least one of the plurality of computation elements is configured to map the bit-oriented operations to the byte-oriented memory and plurality of computation elements.

14. The reconfigurable system of claim 13 further comprising memory for storing programs, and wherein the stored programs comprise instructions for reconfiguring the plurality of computational elements for the channel coding operations.

15. The reconfigurable system of claim 13 wherein each of the plurality of computation elements comprises memory for storing programs, and wherein the stored programs comprise instructions for executing commands for the channel coding operations.

16. The reconfigurable system of claim 13 wherein each of the plurality of polynomial generators further comprises a configuration register, an AND logic means, and an exclusive-OR logic means.

17. The reconfigurable system of claim 13 wherein the plurality of computation elements further comprises a Viterbi decoder element.

18. The reconfigurable system of claim 17 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.

19. A method for providing channel coding in a wireless communication device comprising:

selecting one of a plurality of wireless communication modes within a wireless communication standards; and

reconfigurably controlling a plurality of computation elements for performing channel coding operations to achieve channel coding operations in accordance with the selected wireless communication mode, wherein the plurality of computation elements wherein the plurality of computation elements perform data reordering, perform the operations of a linear feedback shift register (LFSR), and convolutional encoding, and wherein convolutional encoding comprises performing operations of an input shift register, a delay register, a plurality of polynomial generators and an output shift register,

wherein the channel coding operations are bit-oriented and wherein the memory and the plurality of computation elements are byte-oriented, and wherein controlling comprises mapping the bit-oriented operations to the byte-oriented memory and plurality of computation elements.

20. The method of claim 19, further comprising selecting a mode of the selected one of the plurality of wireless communication standards.

21. The method of claim 19, wherein selecting one of the plurality of wireless communication standards comprises:

receiving a signal associated with one of the plurality of wireless communication standards; and

identifying the one of the plurality of wireless communication standards based on the coding of the signal.

22. The method of claim 19, wherein the plurality of computation elements comprises a data reordering element, a linear feedback shift register (LFSR) element, and a convolutional encoder, wherein the convolutional encoder further comprises a coupled configuration of an input shift register, a delay register, a plurality of polynomial generators, and an output shift register.

23. The method of claim 22, wherein the plurality of computation elements further comprises a Viterbi decoder element.

24. The method of claim 19, wherein mapping the bit-oriented operations to the byte-oriented memory and plurality of computation elements comprises processing eight information bits at a time and computing a LFSR state after eight consecutive shifts.