SOLAR CELL AND METHOD OF MANUFACTURING THE SAME

• US 20100032017A1
• Filed: 05/11/2009
• Published: 02/11/2010
• Est. Priority Date: 08/05/2008
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Bae, Joo-Han
• Application Number:
  US12/463,724
• Publication Number:
  US 20100032017A1
• Time in Patent Office: Days
• US Class Current: 136/261
• CPC Class Codes: H01L 31/0475 PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays PV modules composed of a plurality of thin film solar cells deposited on the same substrate H01L31/046
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

In a solar cell and a method of manufacturing the solar cell, when a semiconductor pattern, bottom electrodes and top electrodes are patterned, a first mask pattern having different thicknesses according to location, a second mask pattern formed by etching back the first mask pattern, and a third mask pattern by etching back the second mask pattern are used etch masks. The first mask pattern may be easily manufactured using an imprint method utilizing a mold.

Claims

1. A method of manufacturing a solar cell, the method comprising:

preparing a substrate having a plurality of cell areas and a cell isolation area between two adjacent cell areas;

forming a first conductive layer on the substrate;

forming a semiconductor layer on the first conductive layer;

forming a first mask pattern over the semiconductor layer, wherein the first mask pattern includes at least one first opening corresponding to the cell isolation area;

patterning the semiconductor layer using the first mask pattern to form a preliminary semiconductor pattern, and removing the first conductive layer from the cell isolation area by using the first mask pattern to form bottom electrodes in the cell areas;

etching the first mask pattern to form a second mask pattern having second openings;

patterning the preliminary semiconductor pattern using the second mask pattern to form a semiconductor pattern and to expose the bottom electrodes at locations corresponding to the second openings; and

forming upper electrodes electrically connected with the exposed bottom electrodes on the semiconductor pattern.

2. The method of claim 1, wherein the forming the semiconductor layer comprises:

forming an N type semiconductor layer on the first conductive layer;

forming an intrinsic semiconductor layer on the N type semiconductor layer; and

forming a P type semiconductor layer on the intrinsic semiconductor layer.

3. The method of claim 1, wherein:

the first mask pattern has first to third thicknesses corresponding to first to third areas, respectively,

the second thickness is larger than the first thickness and the third thickness is larger than the second thickness,

the first area corresponds to an area where the top electrodes are formed above the bottom electrodes so that the top electrodes are electrically connected the bottom electrodes,

the second area corresponds to an area where the top electrodes are formed on the semiconductor pattern, and

the third area corresponds to an area where the top electrodes are removed.

4. The method of claim 3, further comprising:

forming an etching assistant layer between the semiconductor layer and the first mask pattern;

etching the etching assistant layer using the first mask pattern to form a first preliminary etching assistant pattern;

etching the first preliminary etching assistant pattern using the second mask pattern to form a second preliminary etching assistant pattern; and

etching the second mask pattern to form a third mask pattern covering the third area.

5. The method of claim 4, wherein the forming the top electrodes comprises:

forming a second conductive layer on an entire surface of the substrate after forming the third mask pattern; and

removing the third mask pattern,

wherein the second conductive layer is formed on the bottom electrodes in the first area so that the second conductive layer is electrically connected with the bottom electrodes, is formed on the semiconductor pattern in the second area, and is formed on the third mask pattern in the third area.

6. The method of claim 3, wherein the forming the first mask pattern comprises:

forming an insulating layer on the first conductive layer;

compressing the insulating layer by using a mold; and

curing the compressed insulating layer by using heat or light.

7. The method of claim 1, wherein the bottom electrodes are formed by an undercut generated in the first conductive layer below the preliminary semiconductor pattern around the first opening.

8. The method of claim 3, wherein the semiconductor pattern is removed from the third area.

9. The method of claim 1, wherein the semiconductor pattern causes a photoelectric effect using energy of light incident through the bottom electrodes.

10. A solar cell comprising:

a substrate having a plurality of cell areas and a cell isolation area between two adjacent cell areas;

a bottom electrode provided on the substrate in each cell area;

a semiconductor pattern provided on the bottom electrodes, wherein a space is defined between the bottom electrodes in the cell isolation area between the two adjacent cell areas; and

a plurality of top electrodes provided on the semiconductor pattern.

11. The solar cell of claim 10, wherein the semiconductor pattern comprises:

an N type semiconductor pattern provided on the bottom electrodes;

an intrinsic semiconductor pattern provided on the N type semiconductor pattern; and

a P type semiconductor pattern provided on the intrinsic semiconductor pattern.

12. The solar cell of claim 10, wherein the top electrodes overlap the two adjacent cell areas.

13. The solar cell of claim 12, wherein a cell area includes a contact hole from which the semiconductor pattern is removed, and a top electrode electrically connected with a bottom electrode through the contact hole.

14. The solar cell of claim 10, wherein the semiconductor pattern has an opening formed in an area where the top electrode is removed.

15. The solar cell of claim 10, wherein the semiconductor pattern causes a photoelectric effect using energy of light incident through the bottom electrodes.

16. A solar cell comprising:

a substrate having a plurality of cell areas and a cell isolation area between two adjacent cell areas;

a bottom electrode provided on the substrate in each cell area;

an undercut section formed in the cell isolation area, wherein the undercut section defines a space between the bottom electrodes in the two adjacent cell areas;

a semiconductor pattern provided on the bottom electrodes; and

a plurality of top electrodes provided on the semiconductor layer.

17. The solar cell of claim 16, wherein a top electrode of the plurality of top electrodes overlaps the two adjacent cell areas.

18. The solar cell of claim 17, further comprising a contact hole formed in the semiconductor pattern, wherein the top electrode is electrically connected to a bottom electrode corresponding to one of the two adjacent cell areas through the contact hole.