HARDWARE TASK MANAGER

• US 20100037029A1
• Filed: 02/09/2009
• Published: 02/11/2010
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: HOGENAUER, Eugene B., SCHEUERMANN, W. James
• Granted Patent: US 8,200,799 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

Claims

1. A computing device comprising:

a plurality of computing nodes;

a memory in at least one of the plurality of computing nodes, the plurality of computing nodes configured to make memory requests for access to the memory;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests;

means for identifying a set of memory requests;

means for determining when all of the memory requests in the set of memory requests have been performed; and

means for initiating execution of a task when all of the memory requests in the set of memory requests have been performed.

2. The computing device of claim 1, wherein the computing device is an integrated circuit.

3. The computing device of claim 1, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

5. The computing device of claim 1, wherein the task is associated with the set of memory requests.

6. The computing device of claim 1, wherein the memory requests are memory write requests.

7. The computing device of claim 1, wherein the task is associated with a plurality of buffers and wherein the memory requests are requests for an availability of the plurality of buffers.

8. The computing device of claim 1, wherein the interconnection network further routes data for the memory requests between the plurality of heterogeneous computing nodes and the memory via a memory controller and routes data among the plurality of heterogeneous computing nodes.

9. The computing device of claim 1 wherein the means for identifying a set of memory requests is a plurality of forward acknowledgement messages and wherein each memory request in the set of memory requests is associated with a port number and each forward acknowledgement message includes a port number and a task number.

10. The computing device of claim 1, wherein the means for determining when all of the memory requests in the set of memory requests have been performed is a ports counter.

11. The computing device of claim 1, wherein the means for initiating execution of a task when all of the memory requests in the set of memory requests have been performed is a ready-to-run queue.

12. A computing device comprising:

a plurality of computing nodes configured to make memory requests for access to a memory in at least one of the plurality of computing nodes;

an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests; and

a task manager in the at least one of the computing nodes configured to identify a set of memory requests, determine when all of the memory requests in the set of memory requests have been performed and initiate execution of a task when all of the memory requests in the set of memory requests have been performed.

4. The computing device of claim 17 wherein the interconnection network is reconfigurable.

13. The computing device of claim 12, wherein the computing device is an integrated circuit.

14. The computing device of claim 12, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

15. The computing device of claim 12, wherein the interconnection network is reconfigurable.

16. The computing device of claim 12, wherein the memory requests are memory write requests.

17. The computing device of claim 12, wherein the task is associated with a plurality of buffers and wherein the memory requests are requests for an availability of the plurality of buffers.

18. The computing device of claim 12, wherein the task manager comprises a ports counter and a ready-to-run queue.

19. The integrated circuit of claim 18, wherein the task manager determines when all of the memory requests have been performed with the port counter.

20. The integrated circuit of claim 18, wherein the task is moved to the ready-to-run queue to initiate execution of the task.

21. A method for managing tasks within a computing device having a plurality of computing nodes configured to make memory requests for access to a memory in at least one of the plurality of computing nodes, and an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes and the memory to route the memory requests, said method comprising:

identifying a set of memory requests;

determining when all of the memory requests in the set of memory requests have been performed; and

initiating execution of a task when all of the memory requests in the set of memory requests have been performed.

22. The method of claim 21, wherein the computing device is an integrated circuit.

23. The method of claim 21, wherein the plurality of computing nodes comprise a plurality of heterogeneous computing nodes.

24. The method of claim 21, wherein the interconnection network is reconfigurable.

25. The method of claim 21, wherein the memory requests are memory write requests.

26. The method of claim 21, wherein the task is associated with a plurality of buffers and wherein the memory requests are requests for an availability of the plurality of buffers.

27. The method of claim 21, wherein identifying a set of memory requests comprises identifying a port number and a task number for each memory request.

28. The method of claim 21, wherein the indicating when all of the memory requests in the set of memory requests have been performed and initiating execution of a task when all of the memory requests in the set of memory requests have been performed is performed by a task manager.