Dummy gate structure for gate last process

• US 20100052060A1
• Filed: 06/03/2009
• Published: 03/04/2010
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chien-Hung, Chang, Hong-Dyi, Cheng, Kuo Cheng, Thei, Kong-Beng, Chuang, Harry Hak-Lay, Lai, Su-Chen, Yeh, Chiung-Han, Wu, Ming-Yuan, Lee, Tzung-Chi
• Granted Patent: US 8,237,227 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first portion and a second portion;

a plurality of transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate;

a device element formed in the second portion of the substrate, the device element being isolated by an isolation region; and

a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.

2. The semiconductor device of claim 1, wherein the device element includes one of a MOS device, a BJT device, a diode, and a resistor.

3. The semiconductor device of claim 1, wherein the polishing stopper includes a dummy poly gate structure.

4. The semiconductor device of claim 1, wherein the polishing stopper covers at least 5% of a pattern density of the second portion of the substrate.

5. The semiconductor device of claim 1, wherein the second portion of the substrate has an area that is at least 20 mm by 20 mm.

6. The semiconductor device of claim 1, wherein polishing stopper is formed on a dummy active region of the substrate.

7. The semiconductor device of claim 1, wherein the polishing stopper is formed on a shallow trench isolation (STI) structure.

8. The semiconductor device of claim 1, wherein the polishing stopper has a size that is substantially not less than a minimum gate size of the transistors formed in the first portion of the substrate.

9. A semiconductor device, comprising:

a semiconductor substrate having a first area and a second area, the first and second areas being isolated from each other;

a plurality of transistors formed in the first area, each transistor including a gate structure with a high-k gate dielectric and a metal gate electrode;

a device element formed in the second area; and

a polishing stopper formed over the substrate and around an edge of the second area, the polishing stopper having a height that is substantially the same as a height of the gate structure of the transistors.

10. The semiconductor device of claim 9, wherein the polishing stopper includes a dummy poly gate structure.

11. The semiconductor device of claim 9, wherein the device element includes one of a MOS device, a BJT device, a diode, and a resistor.

12. The semiconductor device of claim 9, wherein the semiconductor substrate has a third area, the third area being isolated from the first and second areas of the substrate;

wherein the semiconductor device further includes;

one of a monitor pad and an alignment mark formed in the third area of the substrate; and

another polishing stopper formed over the substrate and around an edge of the third area, the another polishing stopper having a height that is substantially the same as the height of the gate structure of the transistors.

13. The semiconductor device of claim 12, wherein the polishing stopper covers at least 5% of a pattern density of the second area of the substrate, and wherein the another polishing stopper covers at least 5% of a pattern density of the third area of the substrate.

14. The semiconductor device of claim 12, wherein the polishing stopper and the another polishing stopper each has a size that is substantially not less than a minimum gate size of the transistors formed in the first area of the substrate.

15. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate having a first portion and a second portion;

forming a plurality of transistors in the first portion of the substrate, each transistor including a dummy gate structure;

forming a device element in the second region, the device element being isolated by an isolation region;

forming a polishing stopper adjacent the isolation region, the polishing stopper being formed in a same process that forms the dummy gate structure of the transistors; and

replacing the dummy gate structure of each transistor with a metal gate.

16. The method of claim 15, further comprising prior to replacing the dummy gate structure, performing a chemical mechanical polishing (CMP) process to expose the dummy gate structure of each transistor;

and

wherein the polishing stopper acts as a stopper in the CMP process.

17. The method of claim 15, wherein the polishing stopper is formed around an edge of the second portion of the substrate.

18. The method of claim 15, wherein the device element includes one of a MOS device, a BJT device, a diode, and a resistor.

19. The method of claim 15, wherein the semiconductor substrate has a third portion, the third portion being isolated from the first and second portions of the substrate;

wherein the method further includes;

forming one of a monitor pad and an alignment mark in the third portion of the substrate; and

forming another polishing stopper over the substrate and around an edge of the third area, the another polishing stopper being formed in the same process that forms the dummy gate structure of the transistors.

20. The method of claim 19, wherein the polishing stopper covers at least 5% of a pattern density of the second area of the substrate, and wherein the another polishing stopper covers at least 5% of a pattern density of the third area of the substrate.