SLEW RATE CONTROLLED LEVEL SHIFTER WITH REDUCED QUIESCENT CURRENT

• US 20100052735A1
• Filed: 08/28/2008
• Published: 03/04/2010
• Est. Priority Date: 08/28/2008
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Burkland, William A., Crandall, Jonathan
• Granted Patent: US 7,679,420 B1
• Time in Patent Office: Days
• US Class Current: 327/66
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror transistor in the other current path, thereby preventing quiescent current during stable periods. An optional cascode transistor is added to facilitate fabrication using low threshold voltage transistors.

Claims

1. A slew rate controlled level shifter circuit for selectively passing a first voltage level from a first voltage source to an output node when an input data signal has a first value, for selectively passing a second voltage level from a second voltage source to the output node when the input data signal has a second value, wherein the level shifter circuit comprises:

a first current path including a first current mirror transistor coupled between the first voltage source and a first node, a first switch transistor coupled between the first node and a second node, and a first slew rate control transistor coupled between the second node and the second voltage source;

a second current path including a second current mirror transistor coupled between the first voltage source and a third node, a third current mirror transistor coupled between the third node and the output node, a second switch transistor coupled between the output node and a fourth node, and a second slew rate control transistor coupled between the fourth node and the second voltage source,

wherein gate terminals of the first and second slew rate control transistors are coupled to a fifth node,

wherein gate terminals of the first and second current mirror transistors are connected to the third node, and a gate terminal of the third current mirror transistor is connected to the first node, and

wherein gate terminals of the first and second switch transistors respectively receive differential control signals.

2. The slew rate controlled level shifter circuit according to claim 1, further comprising a third slew rate control transistor coupled between the fifth node and the second voltage source, wherein a gate terminal of the third slew rate control transistor is coupled to the fifth node such that a gate voltage applied to each of the first, second and third slew rate control transistors is determined by a slew rate control current applied to said fifth node.

3. The slew rate controlled level shifter circuit according to claim 1,

wherein the first, second and third current mirror transistors comprise PHOS transistors, and

wherein the first and second switch transistors and the first and second slew rate control transistors comprise NMOS transistors.

4. The slew rate controlled level shifter circuit according to claim 1, further comprising:

a cascode transistor connected between the first current mirror transistor and the first node.

5. The slew rate controlled level shifter circuit according to claim 4, further comprising:

a first PMOS transistor connected between the first voltage source and a sixth node;

a second PMOS transistor connected between the sixth node and a seventh node; and

first and second NMOS transistors connected in series between the seventh node and the second voltage source,

wherein the gate terminal of the first PMOS transistor is connected to the sixth node,

wherein the gate terminals of the second PMOS transistor and the cascode transistor are connected to the seventh node,

wherein the gate terminal of the second NMOS transistor is connected to the fifth node, and

wherein the gate terminal of the first NMOS transistor is connected to a fixed voltage source.

6. The slew rate controlled level shifter circuit according to claim 1, further comprising:

a third slew rate control transistor coupled between the fifth node and the second voltage source, wherein a gate terminal of the third slew rate control transistor is coupled to the fifth node.

7. A slew rate controlled level shifter circuit for selectively generating a first voltage level on an output node when an input data signal has a first value, for selectively generating a second voltage level on the output node when the input data signal has a second value, and for controlling transitions between the first and second voltage levels in accordance with a selected slew rate determined by a slew rate current source, wherein the level shifter circuit comprises:

a first current path including a first switch transistor and a first slew rate control transistor connected in series between a first node and the second voltage source, wherein the first switch transistor is controlled by the input data signal such that the first switch transistor is opened when the input data signal has the first value, and is closed when the input data signal has the second value; and

a second current path including a second switch transistor and a second slew rate control transistor connected in series between the output node and the second voltage source1 wherein the second switch transistor is controlled by the input data signal such that the second switch transistor is opened when the input data signal has the second value, and is closed when the input data signal has the first value; and

a Wilson current mirror circuit connected to the first and second current paths.

8. The slew rate controlled level shifter circuit according to claim 7, wherein the Wilson current mirror comprises:

a first current mirror transistor coupled in the first current path between the first voltage source and the first node,

second current mirror transistor coupled in the second current path between the first voltage source and a third node, and

a third current mirror transistor coupled in the second current path between the third node and the output node,

wherein gate terminals of the first and second current mirror transistors are connected to the second node, and a gate terminal of the third current mirror transistor is connected to the first node.

9. The slew rate controlled level shifter circuit according to claim 8, further comprising a third slew rate control transistor coupled between a fifth node the second voltage source, wherein a gate terminal of the third slew rate control transistor is coupled to the fifth node such that a gate voltage applied to each of the first, second and third slew rate control transistors is determined by a slew rate control current applied to said fifth node.

10. The slew rate controlled level shifter circuit according to claim 8,

wherein the first, second and third current mirror transistors comprise PMOS transistors, and

wherein the first and second switch transistors and the first and second slew rate control transistors comprise NMOS transistors.

11. The slew rate controlled level shifter circuit according to claim 8, further comprising:

a cascode transistor connected between the first current mirror transistor and the first node.

12. The slew rate controlled level shifter circuit according to claim 11, further comprising:

a first PMOS transistor connected between the first voltage source and a sixth node;

a second PMOS transistor connected between the sixth node and a seventh node; and

first and second NMOS transistors connected in series between the seventh node and the second voltage source,

wherein the gate terminal of the first PMOS transistor is connected to the sixth node,

wherein the gate terminals of the second PMOS transistor and the cascode transistor are connected to the seventh node,

wherein the gate terminal of the second NMOS transistor is connected to the fifth node, and

wherein the gate terminal of the first NMOS transistor is connected to a fixed voltage source.

13. A level shifter circuit for selectively coupling, in response to a data signal, an output node to a first voltage level provided by a first voltage source and a second voltage level provided by a second voltage source such that transitions between the first and second voltage levels are controlled in response to a selected slew rate determined by a slew current source, the level shifter circuit comprising:

a first current mirror including a first current mirror transistor connected between the first voltage source and a first node, a second current mirror transistor connected between the first voltage source and a third node, and a third current mirror transistor connected between the third node and the output node, wherein gate terminals of the first and second current mirror transistors are connected to the third node, and a gate terminal of the third current mirror transistor is connected to the first node;

a slew rate control circuit including a first slew rate control transistor connected between the second voltage source and a second node, a second slew rate control transistor connected between the second voltage source and a fourth node, and a third slew rate transistor connected between the second voltage source and a fifth node wherein gate terminals of the first, second and third slew rate control transistors are coupled to the fifth node, and wherein the fifth node is coupled to the slew current source;

a first switch transistor connected between the first node and the second node; and

a second switch transistor connected between the fourth node and the output node;

wherein the at least one data signal is applied to the gate terminals of the first and second switch transistors.