METHODS AND APPARATUS RELATED TO LOW LATENCY WITHIN A DATA CENTER

• US 20100061240A1
• Filed: 06/30/2009
• Published: 03/11/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Aybay, Gunes, Frailong, Jean-Marc, Sindhu, Pradeep, Vohra, Quaizar, Venkatramani, Anjan
• Granted Patent: US 8,335,213 B2
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. The multi-stage switch fabric has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of edge devices via the set of ingress ports and the set of egress ports. The switch core can be configured to receive a packet from an ingress port from the set of ingress ports. The switch core can be configured to send a set of cells associated with the packet from the ingress port to an egress port from the set of egress ports without a store-and-forward delay associated with a zero-load latency for the switch core.

Claims

1. An apparatus, comprising;

a switch core having a multi-stage switch fabric, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of edge devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to receive a packet from an ingress port from the plurality of ingress ports, the switch core configured to send a plurality of cells associated with the packet from the ingress port to an egress port from the plurality of egress ports without a store-and-forward delay associated with a zero-load latency for the switch core.

2. The apparatus of claim 1, wherein:

the plurality of ingress ports numbers at least 1,000 ports, and

the plurality of egress ports numbers at least 1,000 ports.

3. The apparatus of claim 1, wherein:

the switch core is configured such that a latency for each cell from the plurality of cells is substantially independent of a path within the multi-stage switch fabric of the switch core traversed by that cell when a cabling topology of the switch core is symmetrical and when link of the cabling topology are fully operational.

4. The apparatus of claim 1, wherein:

the switch core configured to send the plurality of cells from the ingress port to the egress port such at the zero-load latency excluding speed-of-light latency or the congestion latency excluding speed-of-light latency is less than 15 μ

sec.

5. The apparatus of claim 1, wherein:

the switch core configured to send the plurality of cells from the ingress port to the egress port such at the zero-load latency excluding speed-of-light latency or the congestion latency excluding speed-of-light latency is less than 10 μ

sec.

6. The apparatus of claim 1, wherein:

the switch core is configured such that the zero-load latency excluding speed-of-light latency and the congestion latency excluding speed-of-light latency each is substantially independent of a location of the ingress port and a location of the egress port,

the multi-stage switch fabric is configured to send the plurality of cells associated with the packet from the ingress port to the egress port substantially without loss.

7. The apparatus of claim 1, wherein:

the egress port is a first egress port,

a latency associated with a second egress port from the plurality of egress port being independent from a latency associated with the first egress port when the first egress port is congested.

8. The apparatus of claim 1, wherein:

the egress port is included in a first subset of egress ports from the plurality of egress ports,

a latency associated with each egress port from a second subset of egress ports from the plurality of egress ports being independent from a latency associated with each egress port from the first subset of egress ports when each egress port from the first subset of egress ports is congested, the first subset of egress ports being mutually exclusive from the second subset of egress ports.

9. An apparatus, comprising;

a switch core having a multi-stage switch fabric, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the switch core configured to be coupled to a plurality of edge devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to receive a packet from each ingress port from the plurality of ingress ports, the switch core configured to send a plurality of cells associated with each packet from the associated ingress port to an associated egress port from the plurality of egress ports such that a latency for each cell is substantially independent of a path within the multi-stage switch fabric of the switch core traversed by that cell when a cabling topology of the switch core is symmetrical and when link of the cabling topology are fully operational.

10. The apparatus of claim 9, wherein:

the plurality of ingress ports numbers at least 1,000 ports, and

the plurality of egress ports numbers at least 1,000 ports.

11. The apparatus of claim 9, wherein the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the egress port without a store-and-forward delay associated with a zero-load latency for the switch core.

12. The apparatus of claim 9, wherein:

the switch core is configured such that the zero-load latency excluding speed-of-light latency and the congestion latency excluding speed-of-light latency each is substantially independent of a location of the ingress port and a location of the egress port,

the multi-stage switch fabric is configured to send the plurality of cells associated with the packet from the ingress port to the egress port substantially without loss.

13. The apparatus of claim 9, wherein:

the egress port is a first egress port,

a latency associated with a second egress port from the plurality of egress port being independent from a latency associated with the first egress port when the first egress port is congested.

14. The apparatus of claim 9, wherein:

the egress port is included in a first subset of egress ports from the plurality of egress ports,

a latency associated with each egress port from a second subset of egress ports from the plurality of egress ports being independent from a latency associated with each egress port from the first subset of egress ports when each egress port from the first subset of egress ports is congested, the first subset of egress ports being mutually exclusive from the second subset of egress ports.

15. An apparatus, comprising;

a switch core having a multi-stage switch fabric, the multi-stage switch fabric having a plurality of ingress ports and a plurality of egress ports, the plurality of ingress ports numbering at least 1,000 ports, the plurality of egress ports numbering at least 1,000 ports, the switch core configured to be coupled to a plurality of edge devices via the plurality of ingress ports and the plurality of egress ports,

the switch core configured to receive a packet from an ingress port from the plurality of ingress ports, the switch core configured to send a plurality of cells associated with the packet from the ingress port to an egress port from the plurality of egress ports such at a zero-load latency excluding speed-of-light latency or a congestion latency excluding speed-of-light latency is less than 15 μ

sec.

16. The apparatus of claim 15, wherein the edge-device-to-edge-device latency is less than 10 μ

sec.

17. The apparatus of claim 15, wherein the switch core is configured to send the plurality of cells associated with the packet from the ingress port to the egress port without a store-and-forward delay associated with the zero-load latency for the switch core.

18. The apparatus of claim 15, wherein:

the switch core is configured such that a latency for each cell from the plurality of cells is substantially independent of a path within the multi-stage switch fabric of the switch core traversed by that cell when a cabling topology of the switch core is symmetrical and when link of the cabling topology are fully operational

19. The apparatus of claim 15, wherein:

the switch core is configured such that the zero-load latency excluding speed-of-light latency and the congestion latency excluding speed-of-light latency each is substantially independent of a location of the ingress port and a location of the egress port,

the multi-stage switch fabric is configured to send the plurality of cells associated with the packet from the ingress port to the egress port substantially without loss.

20. The apparatus of claim 15, wherein:

the egress port is a first egress port,

a latency associated with a second egress port from the plurality of egress port being independent from a latency associated with the first egress port when the first egress port is congested.

21. The apparatus of claim 15, wherein:

the egress port is included in a first subset of egress ports from the plurality of egress ports,

a latency associated with each egress port from a second subset of egress ports from the plurality of egress ports being independent from a latency associated with each egress port from the first subset of egress ports when each egress port from the first subset of egress ports is congested, the first subset of egress ports being mutually exclusive from the second subset of egress ports.