Circuit Having a Low Power Mode

• US 20100064160A1
• Filed: 09/10/2008
• Published: 03/11/2010
• Est. Priority Date: 09/10/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hotelling, Steve Porter, Krah, Christoph Horst, WILSON, Thomas James
• Granted Patent: US 9,189,048 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation.

Claims

1. An integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry connected to the digital interface and configured to perform one or more primary tasks, the primary operation circuitry configured for selectively having substantially all power removed; and

thin power circuitry connected to the primary operation circuitry and the digital input, the thin power circuitry configured to receive a set of one or more predefined digital signals over the digital input while power is removed from the primary operation circuitry, and power up the primary operation circuitry in response to the set of predefined digital signals.

2. The IC of claim 1, wherein the digital interface is configured to transmit and receive digital data according to a predefined digital transmission standard, and the set of predefined digital signals is in accordance with the predefined digital transmission standard.

3. The IC of claim 2, wherein the predefined digital transmission standard is the Serial Peripheral Interface (SPI) standard.

4. The IC of claim 3, wherein the set of predefined digital signals is a valid SPI frame.

5. The IC of claim 2, wherein the predefined digital transmission standard includes one or more standards selected from the group consisting of the low-voltage differential signaling (LVDS), transition minimized differential signaling (TMDS), universal serial bus (USB), Firewire and PCI Express standards.

6. The IC of claim 1, wherein the IC is configured to remove all power from the primary operation circuitry.

7. The IC of claim 1, wherein the thin power circuitry is configured to remove substantially all power from the primary operation circuitry.

8. The IC of claim 1, wherein the thin power circuitry includes a primary state flip flop the primary state flip flop having a first and a second state, the primary state flip flop being in the first state during a first time period when the primary operation circuitry is fully powered and in ordinary operation and in the second state during a second time period when power is removed from the primary operation circuitry, wherein the first and second time periods do not include any transition periods during which the primary operation circuitry is in the process of being powered up, or having power removed therefrom.

9. The IC of claim 8, wherein the primary state flip flop causes the thin power circuitry to ignore signals arriving from the digital input when the primary state flip flop is in the first state and to monitor the digital input for the set of predefined digital signals when the primary state flip flop is in the second state.

10. The IC of claim 1, wherein the digital input includes a plurality of digital connections and the set of predefined digital signals includes a plurality of digital signals received at respective ones of the plurality of digital connections.

11. The IC of claim 1, wherein the thin power circuitry includes one or more inputs connected to the primary operation circuitry, said inputs being used to receive signals indicating an upcoming removal of power from the primary operation circuitry, the thin power circuitry further including one or more resistive pull downs connected to the one or more inputs connected to the primary operation circuitry.

12. The IC of claim 11, wherein the primary operation circuitry is configured to keep the one or more inputs connected to the primary operation circuitry at a low or ground voltage level for most of the time, setting them to a high voltage level only during relatively short pulses.

13. The IC of claim 1, wherein the primary operation circuitry further includes a power manager circuitry, the power manager circuitry being configured to perform complex power up and power down procedures, and to lose substantially all power when substantially all power is removed from the primary operation circuitry.

14. The IC of claim 13, wherein the thin power circuitry uses substantially less power than the power manager circuitry.

15. The IC of claim 1, wherein the thin power circuitry uses substantially less power than the primary operation circuitry.

16. A portable audio player including the IC of claim 1.

17. A mobile telephone including the IC of claim 1.

18. The IC of claim 1, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the thin power circuitry is configured to check the payload portion based on the error checking portion before powering up the primary operation circuitry.

19. A portable audio player including an integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove substantially all power from the primary operation circuitry; and

thin power circuitry connected to the primary operation circuitry and the digital input and configured to

while power is removed from the primary operation circuitry, receive a set of one or more predefined digital signals over the digital input, and

in response to the set of predefined digital signals, power up the primary operation circuitry.

20. A mobile telephone including an integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove substantially all power from the primary operation circuitry; and

thin power circuitry connected to the primary operation circuitry and the digital input and configured to

while power is removed from the primary operation circuitry, receive a set of one or more predefined digital signals over the digital input, and

in response to the set of predefined digital signals, power up the primary operation circuitry.

21. A method for operating an integrated circuit (IC) including primary operation circuitry and thin power circuitry, the method comprising:

powering down the primary operation circuitry while keeping the thin power circuitry powered;

receiving a set of one or more predefined digital signals over a digital input by the power manager circuitry; and

in response to the set of predefined digital signals, powering up the primary operation circuitry by the thin power circuitry.

22. The method of claim 21, wherein the IC includes a digital interface connected to the digital input and configured to transmit and receive digital data according to a predefined digital transmission standard as part of ordinary operation of the IC, and the set of predefined digital signals is in accordance with the predefined digital transmission standard.

23. The method of claim 22, wherein the predefined digital transmission standard is the Serial Peripheral Interface (SPI) standard.

24. The method of claim 23, wherein the set of predefined digital signals is a valid SPI frame.

25. The method of claim 21, wherein powering down the primary operation circuitry includes removing substantially all power from the primary operation circuitry.

26. The method of claim 21, wherein powering down the primary operation circuitry includes removing all power from the primary operation circuitry.

27. The method of claim 21, wherein the powering down the primary operation circuitry is performed at least partially by the thin power circuitry.

28. The method of claim 21, wherein the thin power circuitry includes a primary state flip flop the primary state flip flop having a first and a second state, the primary state flip flop being in the first state during a first time period when the primary operation circuitry is fully powered and in ordinary operation and in the second state during a second time period when power is removed from the primary operation circuitry, wherein the first and second time periods do not include any transition periods during which the primary operation circuitry is in the process of being powered up, or having power removed therefrom.

29. The method of claim 28, further comprising:

ignoring signals arriving from the digital input when the primary state flip flop is in the first state; and

monitoring the digital input for the set of predefined digital signals when the primary state flip flop is in the second state.

30. The method claim 21, wherein the digital input includes a plurality of digital connections and the set of predefined digital signals includes a plurality of digital signals received at respective ones of the plurality of digital connections.

31. The method of claim 21, wherein the thin power circuitry includes one or more inputs connected to the primary operation circuitry, the method further comprising:

receiving signals by the thin power circuitry from the one or more inputs connected to the primary operation circuitry, the signals indicating an upcoming removal of power from the primary operation circuitry;

setting the one or more inputs connected to the primary operation circuitry to a low or ground voltage when the primary operation circuitry is powered down by using resistive pull downs connected to the one or more inputs connected to the primary operation circuitry.

32. The method of claim 31, further including:

keeping the one or more inputs connected to the primary operation circuitry at a low or ground voltage level for most of the time; and

setting them to a high voltage level only during relatively short pulses to indicate an upcoming removal of power from the primary operation circuitry.

33. An integrated circuit (IC) capable of reconfiguration while in a low-power state, the IC comprising:

a configuration memory configured to store configuration information for the IC;

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove substantially all power from the primary operation circuitry; and

thin power circuitry connected to the primary operation circuitry, the digital input and the configuration memory and configured to

while power is removed from the primary operation circuitry, receive a set of one or more predefined digital signals over the digital input, and

in response to the set of predefined digital signals, change the information stored in the configuration memory,

wherein changing the information stored in the configuration memory results in a change of the configuration of the IC.

34. The IC of claim 33, wherein the configuration memory includes core configuration memory.

35. The IC of claim 33, wherein the configuration memory includes I/O configuration memory.

36. The IC of claim 33, wherein the thin power circuitry is configured to use small amount of power in relation to the primary operation circuitry.

37. The IC of claim 33, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the thin power circuitry is configured to check the payload portion based on the error checking portion before changing the information stored in the configuration memory.

38. An integrated circuit (IC) capable of communication with external devices while in a low-power state, the IC comprising:

an external device interface connected to one or more external devices;

a host interface connected to a host;

primary operation circuitry configured to perform one or more primary tasks and connected to the external device interface and the host interface, the IC being configured to selectively remove substantially all power from the primary operation circuitry; and

thin power circuitry connected to the primary operation circuitry, and the external device and host interfaces and configured to

while power is removed from the primary operation circuitry, receive a set of one or more predefined digital signals over the external device interface, and

in response to the set of predefined digital signals, send a signal to the host over the host interface.

39. The IC of claim 38, wherein the host interface is an interrupt interface, and the signal sent to the host over the host interface is an interrupt signal.

40. The IC of claim 38, wherein the external devices are user interface devices.

41. The IC of claim 38, wherein the external devices comprise one or more devices selected from a group consisting of:

a keyboard, a button, a touch sensor, a proximity sensor, and a mouse.

42. The IC of claim 38, wherein the thin power circuitry is configured to use small amount of power in relation to the primary operation circuitry.

43. The IC of claim 38, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the thin power circuitry is configured to check the payload portion based on the error checking portion before sending the signal to the host.

44. The IC of claim 38, wherein the thin power circuitry is further configured to perform the following as part of sending a signal to the host:

generate a set of payload data;

generate a set of error checking data based on the payload data in accordance with a predefined error checking protocol; and

send the payload data along with the error checking data to the host.

45. An integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry connected to the digital interface and configured to perform one or more primary tasks, during a normal power mode of operation of the IC, and to seize operation during a low power mode of operation of the IC, the primary operation circuitry including at least one primary power on reset cell, configured to initialize the primary operation circuitry during a power up of the primary operation circuitry; and

thin power circuitry connected to the primary operation circuitry and the digital input, the thin power circuitry configured to operate during the normal and low power modes of the IC, the thin power circuitry including at least one thin power on reset cell configured to initialize the thin power circuitry during a power up of the thin power circuitry, the thin power on reset cell being distinct from the primary power on reset cell.

46. The IC of claim 45, wherein the thin power on reset cell is configured to use less power during operation than the primary power on reset cell.