PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY

• US 20100074024A1
• Filed: 09/22/2008
• Published: 03/25/2010
• Est. Priority Date: 09/22/2008
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,864,587 B2
• Time in Patent Office: Days
• US Class Current: 365/185.190
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined. The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability.

Claims

1. A method for programming a memory array, the method comprising:

determining a target reliability of data to be programmed; and

programming the data into areas of the memory array wherein the areas are determined in response to the target reliability.

2. The method of claim 1 wherein the areas comprise memory cells of the array that are adjacent to a drain side of the array and adjacent to a source line of the array.

3. The method of claim 1 wherein programming comprises generating at least one programming pulse having an initial programming voltage and any subsequent programming pulses are increased by a step voltage over a previous programming pulse.

4. The method of claim 3 wherein each subsequent programming pulse is preceded by a verify pulse.

5. The method of claim 1 wherein the areas comprise memory cells coupled to a top access line of the array and memory cells coupled to a bottom access line of the array.

6. The method of claim 1 wherein the target reliability is determined in response to a type of data to be programmed.

7. The method of claim 6 wherein the type of data comprises one of data and program code.

8. The method of claim 1 wherein determining comprises receiving user input corresponding to an indication of the target reliability.

9. The method of claim 1 wherein determining comprises performing an algorithm to determine the target reliability.

17. The memory device of claim 6 wherein the memory array comprises a NAND architecture.

10. A method for programming a memory array, the method comprising:

determining high bit error rate areas of the memory array;

determining a type of data to be programmed to the memory array; and

programming the data to areas of the memory array wherein the areas are determined at least partially in response to the high bit error rate areas and the type of data.

11. The method of claim 10 wherein determining the high bit error rate areas comprises performing empirical testing on the memory array to determine which memory cells cannot accurately hold a charge.

12. The method of claim 11 wherein the empirical testing comprises a series of writing and reading operations to the memory array.

13. The method of claim 11 wherein the empirical testing comprises determining how accurately areas of the memory array can be programmed to a target threshold voltage.

14. The method of claim 10 wherein programming the data comprises programming image data to areas of the memory array having a relatively high bit error rate and programming program code data to areas of the memory array having a relatively low bit error rate.

15. The method of claim 10 and further comprising verifying the programming of the data.

16. A non-volatile memory device comprising:

a memory array having relatively low reliability areas of memory cells; and

memory control circuitry for controlling operation of the memory device, the memory control circuitry configured to program the relatively low reliability areas of memory cells with data having relatively low target reliability.

18. The memory device of claim 16 wherein the memory control circuitry is further configured to program data having a relatively high target reliability to areas of memory cells other than the relatively low reliability areas.

19. The memory device of claim 18 wherein the areas of memory cells having the relatively low target reliability comprise memory cells having a high bit error rate.

20. A memory system comprising:

a system controller for controlling operation of the memory system with memory signals; and

a memory device, coupled to the system controller and operating in response to the memory signals, the memory device comprising;

an array of non-volatile memory cells having a first group of memory cells having relatively low reliability and a second group of memory cells having relatively high reliability; and

memory control circuitry coupled to the array of memory cells and configured to accept a type of data to be programmed and generate programming signals to program the data into one of the first group of memory cells or the second group of memory cells in response to both the type of data and the relative reliability of the group of memory cells.

21. The memory system of claim 20 wherein the memory control circuitry is further configured to determine the type of data to be programmed.

22. The memory system of claim 21 wherein the memory control circuitry is further configured to determine whether the data to be programmed is image data or program code data.

23. The memory system of claim 22 wherein the image data is programmed into the first group of memory cells and the program code data is programmed into the second group of memory cells.